VHDL设计的四位抢答器代码
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2011-06-21
12:26:21
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned;
entity vies is
port(sw0,sw1,sw2,sw3,sw4 :in std_logic;
ledhex :out std_logic_vector(6 downto 0));
end vies;
architecture one of vies is
component JK
port(j,k,r,clk :in std_logic;
q,nq :buffer std_logic);
end component;
component andnot
port(a,b,c,d :in std_logic;
x:out std_logic);
end component;
component notgate
port(y :in std_logic;
z :out std_logic);
end component;
component hex
port(a,b,c,d:in std_logic;
hexa:out std_logic_vector(6 downto 0));
end component;
signal e,f,h,i,j:std_logic;
signal g :std_logic;
begin
u1:JK port map(j=>e,k=>e,r=>sw0,clk=>sw1,nq=>g);
u2:JK port map(e,e,sw0,sw2,h);
u3:JK port map(e,e,sw0,sw3,i);
u4:JK port map(e,e,sw0,sw4,j);
u5:andnot port map(a=>g,b=>h,c=>i,d=>j,x=>f);
u6:notgate port map(y=>f,z=>e);
u7:hex port map(g,h,i,j,ledhex);
end one;
--JK program
library ieee;
use ieee.std_logic_1164.all;
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