QNX SDP 6.6 BSP for the Freescale i.XM6 Solo X Sabre SDB

      /*
 * $QNXLicenseC:
 * Copyright 2014, QNX Software Systems.
 *
 * Licensed under the Apache License, Version 2.0 (the "License"). You
 * may not reproduce, modify or distribute this software except in
 * compliance with the License. You may obtain a copy of the License
 * at: http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" basis,
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
 *
 * This file may contain contributions from others, either as
 * contributors under the License or as licensors under other terms.
 * Please review this entire file for other proprietary rights or license
 * notices, as well as the QNX Development Suite License Guide at
 * http://licensing.qnx.com/license-guide/ for other information.
 * $
 */

#include <errno.h>
#include <string.h>
#include <stdio.h>
#include <stdarg.h>
#include <stdlib.h>
#include <malloc.h>
#include <unistd.h>
#include <hw/inout.h>
#include <sys/mman.h>
#include <sys/rsrcdbmgr.h>

#include <internal.h>

#ifdef SDIO_HC_OMAP

#ifdef SDIO_OMAP_BUS_SYNC
#include <arm/mmu.h>
#include <fcntl.h>
#endif

//#define OMAP_DEBUG

#include <omap.h>

static int omap_pwr( sdio_hc_t *hc, int vdd );
static int omap_drv_type( sdio_hc_t *hc, int type );
static int omap_bus_mode( sdio_hc_t *hc, int bus_mode );
static int omap_bus_width( sdio_hc_t *hc, int width );
static int omap_clk( sdio_hc_t *hc, int clk );
static int omap_timing( sdio_hc_t *hc, int timing );
static int omap_signal_voltage( sdio_hc_t *hc, int signal_voltage );
static int omap_cd( sdio_hc_t *hc );
static int omap_pm( sdio_hc_t *hc, int op );
static int omap_cmd( sdio_hc_t *hc, sdio_cmd_t *cmd );
static int omap_abort( sdio_hc_t *hc, sdio_cmd_t *cmd );
static int omap_event( sdio_hc_t *hc, sdio_event_t *ev );
static int omap_tune( sdio_hc_t *hc, int op );
static int omap_preset( sdio_hc_t *hc, int enable );
static int omap_set_dll( sdio_hc_t *hc, int delay );

static sdio_hc_entry_t omap_hc_entry =	{ 16,
										omap_dinit, omap_pm,
										omap_cmd, omap_abort,
										omap_event, omap_cd, omap_pwr,
										omap_clk, omap_bus_mode,
										omap_bus_width, omap_timing,
										omap_signal_voltage, omap_drv_type,
										NULL, omap_tune, omap_preset,
										};

//	EDMA is "Enhanced Direct Memory Access"

//	EDMA initialization
static int edma3_init(const sdio_hc_t *hc);

//	EDMA termination
static int edma3_dinit(edma3_data_t* edma);

//	Setup a scatter receive (transfer from a device I/O port to memory buffers),
//	or a gather transmit (transfer from memory buffers to a device I/O port).
//	Works fine also with just one buffer, so there's no need to have
//	separate code for single buffer I/O.
//
//	Returns 0 if no errors were detected, nonzero otherwise.
//
//	Currently the only possible error is EINVAL - Invalid argument.
//
static int edma3_setup_transfer(
	edma3_data_t* edma,
	unsigned port,	// The data I/O port
	int receiving,	// Nonzero if receiving, zero if transmitting
	unsigned block_size,	// Block size to be used
	const sdio_sge_t* sgp,	// Pointer to the scatter gather fragment descriptors
	unsigned fragment_count	// Number of scatter gather fragments
);

//	Verify that a transfer has really completed.
static void edma3_verify_completion(edma3_data_t* edma);

//	Cleanup at the end of a completed transfer
static void edma3_transfer_done(edma3_data_t* edma);

//	Cleanup at the end of a failed or aborted transfer
static void edma3_transfer_failed(edma3_data_t* edma);

// this is the registers database, per device and per block
typedef struct {
	uint32_t	physbase;		// MC module physical base address
	uint32_t	clkctrl_phys;	// PRCM clkctrl physical address
	uint32_t	context_phys;	// PRCM context register physical address
} pm_info_t;

// Definition of OMAP4 PM info
pm_info_t		omap4_info[] = {
	{ .physbase = MMCHS1_BASE, .clkctrl_phys = OMAP4_MMC1_CLKCTRL, .context_phys = OMAP4_MMC1_CONTEXT },
	{ .physbase = MMCHS2_BASE, .clkctrl_phys = OMAP4_MMC2_CLKCTRL, .context_phys = OMAP4_MMC2_CONTEXT },
	{ .physbase = -1, .clkctrl_phys = -1, .context_phys = -1 },
};

// Definition of OMAP5 ES1 PM info
pm_info_t		omap5_es1_info[] = {
	{ .physbase = MMCHS1_BASE, .clkctrl_phys = OMAP5_ES1_MMC1_CLKCTRL, .context_phys = OMAP5_ES1_MMC1_CONTEXT },
	{ .physbase = MMCHS2_BASE, .clkctrl_phys = OMAP5_ES1_MMC2_CLKCTRL, .context_phys = OMAP5_ES1_MMC2_CONTEXT },
	{ .physbase = MMCHS3_BASE, .clkctrl_phys = OMAP5_ES1_MMC3_CLKCTRL, .context_phys = OMAP5_ES1_MMC3_CONTEXT },
	{ .physbase = MMCHS4_BASE, .clkctrl_phys = OMAP5_ES1_MMC4_CLKCTRL, .context_phys = OMAP5_ES1_MMC4_CONTEXT },
	{ .physbase = MMCHS5_BASE, .clkctrl_phys = OMAP5_ES1_MMC5_CLKCTRL, .context_phys = OMAP5_ES1_MMC5_CONTEXT },
	{ .physbase = -1, .clkctrl_phys = -1, .context_phys = -1 },
};

// Definition of OMAP5 ES2 PM info
pm_info_t		omap5_es2_info[] = {
	{ .physbase = MMCHS1_BASE, .clkctrl_phys = OMAP5_ES2_MMC1_CLKCTRL, .context_phys = OMAP5_ES2_MMC1_CONTEXT },
	{ .physbase = MMCHS2_BASE, .clkctrl_phys = OMAP5_ES2_MMC2_CLKCTRL, .context_phys = OMAP5_ES2_MMC2_CONTEXT },
	{ .physbase = MMCHS3_BASE, .clkctrl_phys = OMAP5_ES2_MMC3_CLKCTRL, .context_phys = OMAP5_ES2_MMC3_CONTEXT },
	{ .physbase = MMCHS4_BASE, .clkctrl_phys = OMAP5_ES2_MMC4_CLKCTRL, .context_phys = OMAP5_ES2_MMC4_CONTEXT },
	{ .physbase = MMCHS5_BASE, .clkctrl_phys = OMAP5_ES2_MMC5_CLKCTRL, .context_phys = OMAP5_ES2_MMC5_CONTEXT },
	{ .physbase = -1, .clkctrl_phys = -1, .context_phys = -1 },
};

pm_info_t		dra7xx_info[] = {
	{ .physbase = MMCHS1_BASE, .clkctrl_phys = DRA7XX_MMC1_CLKCTRL, .context_phys = DRA7XX_MMC1_CONTEXT },
	{ .physbase = MMCHS2_BASE, .clkctrl_phys = DRA7XX_MMC2_CLKCTRL, .context_phys = DRA7XX_MMC2_CONTEXT },
	{ .physbase = MMCHS3_BASE, .clkctrl_phys = DRA7XX_MMC3_CLKCTRL, .context_phys = DRA7XX_MMC3_CONTEXT },
	{ .physbase = MMCHS4_BASE, .clkctrl_phys = DRA7XX_MMC4_CLKCTRL, .context_phys = DRA7XX_MMC4_CONTEXT },
	{ .physbase = -1, .clkctrl_phys = -1, .context_phys = -1 },
};

#ifdef OMAP_DEBUG
static int omap_reg_dump( sdio_hc_t *hc, const char *func, int line )
{
	omap_hc_mmchs_t		*mmchs;
	uintptr_t			base;

	mmchs	= (omap_hc_mmchs_t *)hc->cs_hdl;
	base	= mmchs->mmc_base;

	sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, 1, 1, "%s: line %d", func, line );
	if( hc->cfg.did == OMAP_DID_34XX ) {
		sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, 1, 1, "%s: SYSSTATUS %x, REV %x, CAPA %x, CAPA2 %x, MCCAP %x, SYSTEST %x, FE %x",
			__FUNCTION__,
			in32( base + MMCHS_SYSSTATUS ),
			in32( base + MMCHS_REV ),
			in32( base + MMCHS_CAPA ),
			in32( base + MMCHS_CAPA2 ),
			in32( base + MMCHS_MCCAP ),
			in32( base + MMCHS_SYSTEST ),
			in32( base + MMCHS_FE ) );
	}
	else {
		sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, 1, 1, "%s: HL_REV %x, HL_HWINFO %x, HL_SYSCONFIG %x, SYSSTATUS %x, REV %x, CAPA %x, CAPA2 %x, MCCAP %x, SYSTEST %x, FE %x",
			__FUNCTION__,
			in32( base + MMCHS_HL_REV ),
			in32( base + MMCHS_HL_HWINFO ),
			in32( base + MMCHS_HL_SYSCONFIG ),
			in32( base + MMCHS_SYSSTATUS ),
			in32( base + MMCHS_REV ),
			in32( base + MMCHS_CAPA ),
			in32( base + MMCHS_CAPA2 ),
			in32( base + MMCHS_MCCAP ),
			in32( base + MMCHS_SYSTEST ),
			in32( base + MMCHS_FE ) );
	}

	sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, 1, 1, "%s: CSRE %x, CON %x, PWCNT %x, BLK %x, ARG %x, CMD %x, RSP10 %x, RSP32 %x, RSP54 %x,  RSP76 %x",
		__FUNCTION__,
		in32( base + MMCHS_CSRE ),
		in32( base + MMCHS_CON ),
		in32( base + MMCHS_PWCNT ),
		in32( base + MMCHS_BLK ),
		in32( base + MMCHS_ARG ),
		in32( base + MMCHS_CMD ),
		in32( base + MMCHS_RSP10 ),
		in32( base + MMCHS_RSP32 ),
		in32( base + MMCHS_RSP54 ),
		in32( base + MMCHS_RSP76 ) );

	sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, 1, 1, "%s: PSTATE %x, HCTL %x, SYSCTL %x, STAT %x, IE %x, ISE %x, AC12 %x, ADMAES %x ADMASAL %x",
		__FUNCTION__,
		in32( base + MMCHS_PSTATE ),
		in32( base + MMCHS_HCTL ),
		in32( base + MMCHS_SYSCTL ),
		in32( base + MMCHS_STAT ),
		in32(