MT9V034寄存器版数据手册

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MT9V034寄存器配置详细说明,参考手册,MT9V034-Register Reference
Aptina Confidential and Proprietary △ptna MT9V034: 1/ 3-Inch Wide -VGA Digital Image Sensor Table of contents Changes to Integration Time Exposure Indicator ::::.·:·:: ....54 High Dynamic Range 54 ADC Companding mode. ,,,,,,,,56 Gain settings ···...··· ·:·.·······:·· ∴.....57 Changes to gain settings 57 Analog gain.... 58 Digital gain 58 Black level calibration 59 Row-wise noise Correction ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,..61 Automatic Gain Control and Automatic Exposure Control...................... 61 Pixel Clock speed .,62 Hard reset of logic ··.·······.·::·.········:·· ··:···.··:·:···· ,,,,,,,,,,,63 Soft reset of logic.................. ........63 STANDBY Control ........63 Monitor mode control 63 Rcad Modc Options ,63 Column fli ,,,,,,63 Row Flip ················· 64 Pixel Binning.…… 64 Row Binning.......... 垂章垂 ··· 65 Column binning ...65 Interlaced readout 66 LINE VALID ,,,,68 LVDS Serial(Stand-Alone/Stereo) Output 68 LVDS Output Format 69 LVDS Enablc and disable ,,,,,,,,,,,,71 LVDS Data Bus Timing ∴,,,,,,,,,,,,,,,,,,,,.,72 Electrical Specifications Propagation Delays for PiXClK and data Out Signals............... Propagation Delays for FRAME- VALID and LiNE- VALID Signals 355 Two-Wire serial bus timi 76 Minimum Master Clock Cycles∴∴.,,,………,……… Package Dimensions 80 Appendix a- Power-On Reset and Standby timing .81 Revision history. 82 09005aef8366edcb/Source: 03005aef8366edes 9VC34 DS. Rev. A 10/08 EN @2008 Aptina Imaging Corporation All rights reserved Aptina Confidential and Proprietary △ptna MT9V034: 1/ 3-Inch Wide-VGA Digital Image Sensor List of Figures List of Figures Figure 1 Block Diagram Figure 2: 48-Pin CLCC Package Pinout Diagram 7 Figurc 3: Typical Configuration(Connection)Parallcl Output Mode. Figure 4: Pixel Array Description 10 Figure 5: Pixel Color Pattern Detail (Top Right Corner Figure 6 Spatial lllustration oflmage readout.,.……, ,,12 Figure 7: Timing Example of Pixel Data 翻 Figure 8: Row Timing and FRAME- VALID/LINE- VALID Signals ·· 13 Figure 9: Timing Diagram Showing a Write to ROXo9 with the Value 0x0284..............17 Figure 10: Timing Diagram Showing a Read from ROX09; Returned Value 0x0284 ,,,,17 Figure 11: Timing Diagram Showing a Bytewise Write to ROx09 with the Value 0x0284 18 Figurc 12: Timing Diagram Showing a Bytcwisc Rcad from ROx09; Rcturncd valuc 0x0284 ,,18 Figure 13: Simultaneous Master Mode Synchronization Waveforms #1 47 Figure 14: Simultaneous Master Mode Synchronization Waveforms #2 48 Figure 15: Sequential Master Mode Synchronization Waveforms 48 Figure 16: Snapshot Mode interface Signals 49 Figure 17: Snapshot Mode Frame Synchronization Waveforms 49 Figure 18: Slave Mode Operation Figure 19: Signal Path 50 Figure 20: Latency When Changing Integration ········ 53 Figurc 21: Scqucncc of Control Voltages at thc HDR Gatc 4 Figure 22: Sequence of Voltages in a Piecewise Linear Pixel Response ,,55 Figure 23: 12-to 10-Bit Companding Chart ,,,,56 ure 24: Latency of Analog gain Change When AGC Is Disabled ,,,,,,,,,,,,,57 Figure 25: Tiled Sample.... .···...·.· Figure 26: Black Level Calibration Flow Chart · 59 Figure 27: Controllable and Observable AEC/AGC Registers 62 Figure28: Readout of Six Pixels in Normal and Column Flip Output Mode.∴.…….,………,64 Figure 29: Readout of Six rows in Normal and Row Flip Output Mode................. 64 Figure 30: Readout of 8 Pixels in Normal and row Bin Output Modc 65 Figure 31: Readout of 8 Pixels in Normal and Column Bin Output Mode. ·.··· 66 Figure 32: Spatial Illustration of Interlaced Image Readout 67 Figure 33: Different LINE VALID Formats........... 68 Figure 34: Serial Output Format for a 6x2 Frame ,,69 Figure 35: LVDS Timing Figure 36: Propagation Delays for PIXCLK and Data Out Signals Figure37: Propagation Delays for FRAME- VALID and LiNE_ VALID Signal!.…………75 Figure 38: Two-wire Serial Bus Timing 76 Figure 39: Serial Host Interface Start Condition Timing Figure 40: Serial Host Interface Stop Condition Timing........................77 Figure 41: Serial Host Interface Data Timing for Write............... Figure 42: Serial Host Interface Data Timing for read ,,78 Figure 43: Acknowledge Signal Timing After an 8-Bit WRITE to the Sensor ,,,,,,,,,,78 Figure 44: Acknowledge Signal Timing After an 8-Bit READ from the Sensor 78 Figure45: Typical Quantum Efficiency- Color,……………… Figure 46: Typical Quantum Efficiency -Monochrome 79 Figure47:48- Pin ClCC Package Outline drawing.∴………………∴80 Figure 48: Power-up, Reset, Clock and Standby Sequence 81 09005aef8366edcb/Source: 03005aef8366edes Aptina Imaging reserves the right to change products or specifications without notice 9VC34 DS. Rev. A 10/08 EN @2008 Aptina Imaging Corporation All rights reserved Aptina Confidential and Proprietary △ptna MT9V034: 1/ 3-Inch Wide-VGA Digital Image Sensor List of tables List of tables Table 1. Key performance Parameters Table 2. Available part numbers Table 3 Pin Descriptions 8 Table 4 Frame time ····· 13 Tablc 5: Framc Timc--Long Intcgration Timc 14 Table 6 Slave Address modes ::···. ,,,,,,,,,,,,,,,16 Table 7 Real-Time Context-Switchable Registers 20 Table 8 Default Register Descriptions.∴∴,,,,,,,,,,,…,,,,,…,,,2l Table 9 Register Descriptions............. ·······: Table 1o LVDS Packet format in stand-Alone mode 69 Table1l: LVDS Packet Format in Stereoscopy Mode( Stereoscopy Mode Bit Asserted).∴…………………70 Table 12: reserved words in the pixel data stream 70 Table13:SER_ DATAOUT* state∴,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ........71 Table 14: shft clk state 71 Tablc 15: LVDS AC Timing specifications ..·····:·: Table 16: DC Electrical Characteristics Over Temperature............ Table 17: Dc electrical characteristics Table 18: Absolute Maximum Ratings 74 Table 19: Ac electrical characteristics 74 Table 20: Two-Wire Serial Bus Timing Parameters 76 09005aef8366edcb/Source: 03005aef8366edes Aptina Confidential and Proprietary △ptna MT9V034: 1/ 3-Inch Wide-VGA Digital Image Sensor General Description General Description The mr9v034 is a 1/3-inch widc-VGA format CMOS actiVc-pixcl digital image sensor with TrueSNaPTM global shutter and high dynamic range(HDR)operation. The sensor has specifically been designed to support the demanding interior and exterior surveil lance imaging needs, which makes this part ideal for a wide variety of imaging applica tions in real-world environments This wide- VGa CMOS image sensor features DigitalClarity--Aptina's breakthrough low-noisc CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of cmos The activc imaging pixel array is 752H x 480V. It incorporates sophisticated camera func tions on-chip--such as binning 2 x2 and 4 x4, to improve sensitivity when operating in smaller resolutions--as well as windowing, column and row mirroring. It is program mable through a simple two-wire serial interface The mt9v034 can be operated in its default mode or be programmed for frame size, exposure, gain setting, and other parameters. The default mode outputs a widc-VGA-sizc image at 60 frames per second (fps) An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. A 12-bit resolu tion companded for 10 bits for small signals can be alternatively enabled, allowing more accurate digitization for darker areas in the image In addition to a traditional, parallel logic output the mt9v034 also features a serial low- voltage differential signaling(LVDS)output. The sensor can be operated in a stereo camera, and the sensor, designated as a stereo- master, is able to merge the data from itself and the stereo-slave sensor into one serial lvds stream The sensor is designed to operate in a wide temperature range (-30@C to +70C) Figure 1: Block Diagram Control Registe gist 1/O Active-Pixel Ar 752Hx480V Timing and control Analog Processing Parallel ADCs Digital Processing HI/- Vide Data Out Serial vide Slave video lvds in LVDS Out (for stereo applications only) 09005aef8366edcb/Source: 03005aef8366edes Aptina Imaging reserves the right to change products or specifications without notice 9VC34 DS. Rev. A 10/08 EN @2008 Aptina Imaging Corporation All rights reserved Aptina Confidential and Proprietary △ptna MT9V034: 1/ 3-Inch Wide-VGA Digital Image Sensor General Description Figure 2: 48-Pin CLCC Package Pinout Diagram 555 可可 舌98苏 × LVDSGND 一DoUT3 BYPASS CLKIN N口8 DOUT4 BYPASS CLKIN P□9 0 VAAPIX SER DATA|NN□10 39一VAA SER DATAIN P口1 AGND LVDSGND NO VDD VAA DOUT5 AGND DoUT6口16 33 STANDBY DOUT7 RESET BAR DoUT8□18 S CTRL ADR1 上卜 乏 09005aef8366edcb/Source: 03005aef8366edes 7 Aptina Imaging reserves the right to change products or specifications without notice Aptina Confidential and Proprietary △ptna MT9V034: 1/ 3-Inch Wide-VGA Digital Image Sensor Pin Descriptions Pin Descriptions Table 3: Pin Descriptions 48-Pin ClCC Numbers Symbol Tvpe Description Note 29 RSVD Input Connect to DGND. 1 10 SER DATAIN N Serial data in for stereoscopy(differential negative). Tie to lKQ2 pull-up(to 3.3V)in non-stereoscopy mode 11 SER DATAIN P Input Serial data in for stereoscopy(differential positive). Tie to DGND in non-stereoscopy mode BYPASS CLKIN N Input Input bypass shift-CLK (differential negative). Tie to 1KQ2 pull-up (to 3. 3V) in non-stereoscopy mode BYPASS CLKIN P nput bypass shift-CLK (differential positive). Tie to DGND in non stereoscopy mode 23 EXPOSURE nput Rising edge starts exposure in snapshot and slave modes. 25 SCLK Input Two-wire serial interface clock. Connect to ydd with 1,5K resistor even when no other two-wire serial interface peripheral is attached 28 OE Inpu DOUT enable pad, active HIGH S CTRL ADRO Input Two-wire serial interface slave address select (see Table 6 on page 16 31 S CTRL ADR1 Two-wire serial interface slave address select see table 6 on age 16 32 RESET BAR Input Asynchronous reset All registers assume defaults 33 STANDBY Input Shut down sensor operation for power saving 47 SYSCLK Input Master clock(26.6 MHZ; 13 MHz-27 MHz) 24 SDATA lO Two-wire serial interface data. Connect to VdD with 1.5K resistor even when no other two-wire serial interface peripheral is attached 22 STLN OUT 1/O Output in master mode -start line sync to drive slave chip in phase; input in slave mode STERM OUT lO Output in master mode--start frame sync to drive a slave chip in phase: input in slave mode 20 LINE_VALID Output Asserted when DouT data is valid. FRAME VALID Output Asserted when DouT data is valid. 15 DOUT5 Output Parallel pixel data output 5 16 DOUT6 Output Parallel pixel data output 6 17 DOUT7 Output Parallel pixel data output 7 18 DOUT8 Output Parallel pixel data output 8 19 DOUT9 Output Parallel pixel data output 9 27 LED OUT Output LED strobe output 41 DOUT4 Outp Parallel pixel data output 4 42 DOUT3 Output Parallel pixel data output 3 43 DOUT2 p Parallel pixel data output 2 4 DOUT1 Output Parallel pixel data output 1 45 DOTO Output Parallel pixel data output O 46 PIXCLK Output Pixel clock out douT is valid on rising edge of this clock. I SHFT_ CLKOUT_N Output Output shift CLK( differential negative SHFT CLKOUT P Output Output shift CLK(differential positive). 4 SER_DATAOUT_N Output Serial data out(differential negative). 09005aef8366edcb/Source: 03005aef8366edes 9VC34 DS. Rev. A 10/08 EN @2008 Aptina Imaging Corporation All rights reserved Aptina Confidential and Proprietary △ptna MT9V034: 1/ 3-Inch Wide-VGA Digital Image Sensor Pin Descriptions Table 3: Pin Descriptions(continued) 48-Pin CLCO Numbers Symbol Type Description Note 5 SER_DATAOUT_P Output Serial data out(differential positive). 1.14 VDD Suppl Digital power 3.3V 35,39 VAA Supply Analog power 3.3V. 40 VAAPIX upply Pixel power 3. 3V. 6 VDDLVDS Supply Dedicated power for LVDS pads 7,12 LVDSGND Ground Dedicated GND for LVDS pads 13,48 DGND Ground Digital GND 34,38 AGND Ground Analog gnd 36,37 NO NC No connect Notes: 1. Pin 29, (RSVD) must be tied to GND 2. Output enable(oe)tri-states signals DOUTO-DOUT9, LINE VALID, FRAME VALID, and PIXCLK 3. No connect. These pins must be left floating for proper operation Figure 3: Typical Configuration( ConnectionParallel Output Mode VDD VAAPⅨX VDDLVDS VDD VAA VAAPIX Master clock SYSCLK DOUT(9: 0) LINE VALID ↓ To controller RESET BAR FRAME VALID STANDBY fro EXPOSURE PIXCLK controller or STANDBY digital GND S CTRL ADRO LED OUT To LEd output S CTRL ADR1 TWo-wire SCLK serial interface SDATA RSVD DGND LVDSGND AGND 0.1uF LvDS signals are to be left floating 09005aef8366edcb/Source: 03005aef8366edes 9VC34 DS. Rev. A 10/08 EN @2008 Aptina Imaging Corporation All rights reserved Aptina Confidential and Proprietary △ptna MT9V034: 1/ 3-Inch Wide-VGA Digital Image Sensor Pixel data Format Pixel data Format Pixel Array Structure The mT9 V034 pixel array is configured as 809 columns by 499 rows, shown in Figure 4 The dark pixels are optically black and are used internally to monitor black level Of the left 52 columns, 36 are dark pixels used for row noise correction. Of the top 14 rows of pixels, two of the dark rows are used for black level correction. Also, three black rows from the top black rows can be read out by setting the Show Dark rows bit in the read Mode register; setting Show Dark Columns will display the 36 dark columns. There are 753 columns by 481 rows of optically active pixels. While the sensor's format is 752 X 480, one additional active column and active row are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. This one pixel adjustment is always performed, for monochrome or color versions. The active arca is surrounded with optically transparent dummy pixels to improve image unifor mity within the active area. Neither dummy pixels nor barrier pixels can be read out Figure 4: Pixel Array Description 0,0) active pixel 2 barrier +8(2+4 addressed+ 2)dark+2 barrier +2 light dummy 492x3.05mm2 Pixel Array light dummy pix×el 809X499(753×481 active) 6.0um pixel dark pixel 3 barrier +38(1+36 addressed +1) dark +9 barrier +2 light dummy 2 barrier +2 light dummy 2 barrier 2 light dummy barrier pixel 09005aef8366edcb/Source: 03005aef8366edes 9VC34 DS. Rev. A 10/08 EN 10 @2008 Aptina Imaging Corporation All rights reserved

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