`timescale 1ns/1ps
module dcls_decode_tb;
reg clk_1M;
reg rst_n;
reg dcls_in;
wire [ 6: 0] sec;
wire [ 6: 0] min;
wire [ 5: 0] hur;
wire [ 9: 0] day;
wire [ 7: 0] year;
initial
begin
rst_n=0;
#1000
rst_n=1;
end
initial
begin
clk_1M = 1;
while(1)
//#1000000 clk_1M = ~clk_1M ;
#500 clk_1M = ~clk_1M ;
end
//**************?=37*************
//**************?=67*************
//**************??=22***********
//**************?=363************
//**************?=61*************
initial
begin
//*******************sec*********************
while(1)begin
#1000 dcls_in = 1;
#1000 dcls_in = 1;
#1000 dcls_in = 1;
#1000 dcls_in = 1;
#1000 dcls_in = 1;
#1000 dcls_in = 1;
#1000 dcls_in = 1;
#1000 dcls_in = 1;
#1000 dcls_in = 0;
#1000 dcls_in = 0;//0
