FPGA使用VGA显示，verilog代码

module VGA(clock,disp_dato,hsync,vsync);
input clock; //50MHz
output  [7:0]disp_dato; //VGA_output_data
output hsync; //VGA_row_clk
output vsync; //VGA_list_clk

reg [9:0]hcount; //VGA_row_scan_clk
reg [9:0]vcount; //VGA_field_scan_clk
reg [7:0]data;
reg [7:0]h_dat;
reg [7:0]v_dat;
reg [9:0]timer;
reg flag;
wire hcount_ov;
wire vcount_ov;
wire dat_act;
wire hsync;
wire  vsync;
wire vga_clk;
//VGA_row,field_scan
parameter hsync_end  = 10'd95,
hdat_begin = 10'd143,
hdat_end = 10'd783,
hpixel_end = 10'd799,
vsync_end = 10'd1,
vdat_begin = 10'd34,
vdat_end = 10'd514,
vline_end = 10'd524;

//PLL