十进制频率计FPGA程序，verilog代码

module frequency(clock,freq_input,dig,seg,test);
input  clock;
input  freq_input;    
output[5:0] dig;
output[7:0] seg;
output[9:0] test;

reg [25:0]  counter;    
reg [31:0]  freq_result;    
wire[31:0]  pre_freq;           
reg rst;
wire     divide_clk;
wire  clk_scan;

wire cout1,cout2,cout3,cout4,cout5,cout6,cout7;

assign clk_scan = counter[5];
assign test = counter[9:0];

always @(posedge clock)         
begin
if (divide_clk)
     counter <= 26'd0;
  else
     counter <= counter + 1'b1;
end
assign divide_clk = (counter >= 26'd20000000);

always @(posedge clock)       
begin