a-Si TFT LCD Single Chip Driver
320RGBx480 Resolution and 262K color
ILI9481
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 3 of 143 Version: 0.21
8.2.20.
Read_memory_start (2Eh) .................................................................................................. 66
8.2.21. Set_partial_area (30h)......................................................................................................... 68
8.2.22. Set_scroll_area (33h) .......................................................................................................... 71
8.2.23. Set_tear_off (34h)................................................................................................................ 76
8.2.24. Set_tear_on (35h)................................................................................................................ 77
8.2.25. Set_address_mode (36h).................................................................................................... 79
8.2.26. Set_scroll_start (37h) ..........................................................................................................82
8.2.27. Exit_idle_mode (38h)........................................................................................................... 84
8.2.28. Enter_idle_mode (39h)........................................................................................................ 85
8.2.29. Set_pixel_format (3Ah)........................................................................................................ 87
8.2.30. Write_Memory_Continue (3Ch)........................................................................................... 89
8.2.31. Read_Memory_Continue (3Eh)........................................................................................... 91
8.2.32. Set_Tear_Scanline (44h)..................................................................................................... 93
8.2.33. Get_Scanline (45h)..............................................................................................................94
8.2.34. Read_DDB_Start (A1h) ....................................................................................................... 95
8.2.35. Command Access Protect (B0h) ......................................................................................... 97
8.2.36. Low Power Mode Control (B1h) .......................................................................................... 98
8.2.37. Frame Memory Access and Interface Setting (B3h) ........................................................... 99
8.2.38. Display Mode and Frame Memory Write Mode Setting (B4h)........................................... 101
8.2.39. Device Code Read (BFh) .................................................................................................. 102
8.2.40. Panel Driving Setting (C0h) ............................................................................................... 103
8.2.41. Display_Timing_Setting for Normal Mode (C1h)............................................................... 107
8.2.42. Display_Timing_Setting for Partial Mode (C2h) ................................................................ 109
8.2.43. Display_Timing_Setting for Idle Mode (C3h)......................................................................111
8.2.44. Frame Rate and Inversion Control (C5h) .......................................................................... 113
8.2.45. Interface Control (C6h) ...................................................................................................... 114
8.2.46. Gamma Setting (C8h)........................................................................................................ 115
8.2.47. Power_Setting (D0h) ......................................................................................................... 116
8.2.48. VCOM Control (D1h) ......................................................................................................... 118
8.2.49. Power_Setting for Normal Mode (D2h) ............................................................................. 120
8.2.50. Power_Setting for Partial Mode (D3h)............................................................................... 122
8.2.51. Power_Setting for Idle Mode (D4h) ................................................................................... 124
8.2.52. NV Memory Write (E0h) .................................................................................................... 126
8.2.53. NV Memory Control (E1h) ................................................................................................. 127
8.2.54. NV Memory Status Read (E2h) ......................................................................................... 128
8.2.55. NV Memory Protection (E3h) ............................................................................................ 129
9. Display Data RAM..................................................................................................................................... 129
9.1. Configuration................................................................................................................................ 129
9.2. Memory to Display Address Mapping .......................................................................................... 131