M25P64型flash的Verilog读写代码

module flash_control(clk,reset,flash_q,wr,addr_wrf,data_wrf,rd,addr_rdf,
flash_c,flash_w,flash_h,flash_s,flash_d,fs,dataout,req_data,state);
input clk;
input reset;
input flash_q;
input wr; //往flash写数据的使能，上升沿有效
input [23:0] addr_wrf; //写flash的首地址
input [15:0] data_wrf; //写flash的数据，延迟req_data一个时钟
input rd; //从flash读数据的使能，上升沿有效
input [23:0] addr_rdf; //读flash的首地址，此程序一次读2048个数据，可自行更改

output flash_c;
output flash_w;
output flash_h;
output reg flash_s;
output reg flash_d;

output reg fs; //读使能rd给过后从flash读出的真实数据帧信号
output reg [15:0] dataout; //读使能rd给过后从flash读出的真实数据，与fs对齐
output reg req_data; //flash擦除完毕需要给flash数据，req_data为写数据请求信号，提前data_wrf一个时钟

output [5:0] state;
reg [5:0] state=6'b00000;

reg aux_wr;
reg aux_rd;
reg wip;
reg [23:0] i;
reg [3:0] j1;
reg [3:0] j2;

reg [3:0] j3;
reg [3:0] k;
reg [1:0] state_addr;
reg [7:0] addr_H;
reg [7:0] addr_M;
reg [7:0] addr_L;
reg [23:0] addr_se;
reg [23:0] addr_pp;

reg [7:0] read_q;
reg [23:0] addr_rd;
reg fs1;
reg fs2;
reg [15:0] dataout1;
reg [15:0] dataout2;
reg [3:0] count_q;
reg [23:0] r;

assign flash_c = clk;
assign flash_w = 1'b1;
assign flash_h = 1'b1;

parameter p_wren =8'b0000_0110,
          p_rdsr =8'b0000_0101,
          p_pp =8'b0000_0010,
          p_ce =8'b0110_0000,
    p_be =8'b1101_1000,
 p_read_q=8'b0000_0011;
 
always@(posedge clk)