一段NOR FLASH 控制器的Verilog源码,自己学习用
module flash_controller(
input clk,
input reset_b,
input module_enable,
output [127:0] string,
output ready,
output [20:1] a,
output flash_ce_b,
output we_b,
output oe_b,
inout [15:0] d
);
wire resetb_b = (reset_b & module_enable);
reg [19:0] adr;
reg [15:0] data;
reg t_oe_b;
reg t_we_b;
reg t_flash_ce_b;
// write test data to the whole flash
reg [15:0] received_data;
reg [15:0] polling_data;
reg [3:0] wr_state;
reg [3:0] erase_state;
reg stop_writing_0;
reg stop_writing_1;
reg stop_erasing_1;
reg stop_erasing_2;
reg [3:0] wcnt;
reg [3:0] ecnt;
//reg [18:0] wr_word_adr;
reg [19:0] wr_word_adr;
reg [15:0] wr_word_data;
reg [23:0] err_cnt;
reg [29:0] delay;
reg erase_error;
reg read_error;
wire erase_finished = &delay;
reg last_chance;
reg [7:0] wr_errors;
reg otkl;
wire ERASE1 = ~stop_erasing_1 & ~stop_writing_1 & ~stop_erasing_2 & ~stop_writing_0;
wire ERASE2 = stop_erasing_1 & stop_writing_1 & ~stop_erasing_2 & ~stop_writing_0;
wire WRITE1 = stop_erasing_1 & ~stop_writing_1 & ~stop_erasing_2 & ~stop_writing_0;
wire WRITE2 = stop_erasing_1 & stop_writing_1 & stop_erasing_2 & ~stop_writing_0;
always @(posedge clk) begin
if (~resetb_b) begin
wr_state = 0;
erase_state = 0;
t_oe_b <= 1;
t_we_b <= 1;
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