REV 1.2 according to Datasheet M25P16 REV 2.0 (24 November 2003)
=======================================================================================
WARNING : These Verilog models are provided "as is" without warranty of any kind,
including, but not limited to, any implied warranty of merchantability and fitness
for a particular purpose.
=======================================================================================
PROJECT ARCHITECTURE
Parameter.v
|
TestBench.v
|--------------> M25Pxx.v
| |--------------> memory_access.v
| |--------------> internal_logic.v
| |--------------> acdc_check.v
| |--------------> parameter.v
|
|--------------> M25Pxx_driver.v
The project should be compiled in the following order :
- parameter.v : define all constants
- memory_access.v : perform read/write operations
- internal_logic.v : describe internal working
- acdc_check.v : check if timings respect datasheet.
- m25pxx.v : external description of Serial Flash
- m25pxx_driver.v : stimuli + library of operations example
- testbench.v : a testbench example
TECHNICAL SUPPORT
For current information on M25Pxx products, please consult our pages on the world wide web:
www.st.com/eeprom
If you have any questions or suggestions concerning the matters raised in this document, please send
them to the following electronic mail addresses:
apps.eeprom@st.com (for application support)
ask.memory@st.com (for general enquiries)
M25P16_verilog仿真模型.rar （13个子文件） 
M25P16_verilog仿真模型 M25Pxx仿真模型（verilog）亲测可用 
initmemory.txt 6.02MB
testbench.v 931B parameter.v 3KB M25p16.v 1KB internal_logic.v 50KB m25p16_driver.v 45KB
converter1.1.exe 172KB release notes.txt 3KB acdc_check.v 10KB
m25 user man.pdf 83KB initM25P16.txt 6.02MB memory_access.v 6KB readme.txt 2KB资源评论
