MODERN PROCESSOR DESIGN
3.4 Memory Hierarchy 110
3.4.1 Components of a Modem Memory Hierarchy 111
3.4.2 Temporal and Spatial Locality 113
3.4.3 Caching and Cache Memories 115
3.4.4 Main Memory 127
3.5 Virtual Memory Systems 136
3.5.1 Demand Paging 138
3.5.2 Memory Protection 141
3.5.3 Page Table Architectures 142
3.6 Memory Hierarchy Implementation 145
3.7 Input/Output Systems 153
3.7.1 Types of I/O Devices 154
3.7.2 Computer System Busses 161
3.7.3 Communication with I/O Devices 165
3.7.4 Interaction of I/O Devices and Memory Hierarchy 168
3.8 Summary 170
4 Superscalar Organization 177
4.1 Limitations of Scalar Pipelines 178
4.1.1 Upper Bound on Scalar Pipeline Throughput 178
4.1.2 Inefficient Unification into a Single Pipeline 179
4.1.3 Performance Lost Due to a Rigid Pipeline 179
4.2 From Scalar to Superscalar Pipelines 181
4.2.1 Parallel Pipelines 181
4.2.2 Diversified Pipelines 184
4.2.3 Dynamic Pipelines 186
4.3 Superscalar Pipeline Overview 190
4.3.1 Instruction Fetching 191
4.3.2 Instruction Decoding 195
4.3.3 Instruction Dispatching 199
4.3.4 Instruction Execution 203
4.3.5 Instruction Completion and Retiring 206
4.4 Summary 209
5 Superscalar Techniques 217
5.1 Instruction Flow Techniques 218
5.1.1 Program Control Flow and Control Dependences 218
5.1.2 Performance Degradation Due to Branches 219
5.1.3 Branch Prediction Techniques 223
5.1.4 Branch Misprediction Recovery 228
5.1.5 Advanced Branch Prediction Techniques 231
5.1.6 Other Instruction Flow Techniques 236
5.2 Register Data Flow Techniques 237
5.2.1 Register Reuse and False Data Dependences 237
5.2.2 Register Renaming Techniques 239
5.2.3 True Data Dependences and the Data Flow Limit 244
TABLE OF CONTENTS
5.2.4 The Classic Tomasulo Algorithm 246
5.2.5 Dynamic Execution Core 254
5.2.6 Reservation Stations and Reorder Buffer 256
5.2.7 Dynamic Instruction Scheduler 260
5.2.8 Other Register Data Flow Techniques 261
5.3 Memory Data Flow Techniques 262
5.3.1 Memory Accessing Instructions 263
5.3.2 Ordering of Memory Accesses 266
5.3.3 Load Bypassing and Load Forwarding 267
5.3.4 Other Memory Data Flow Techniques 273
5.4 Summary 279
6 The PowerPC 620 301
6.1 Introduction 302
6.2 Experimental Framework 305
6.3 Instruction Fetching 307
6.3.1 Branch Prediction 307
6.3.2 Fetching and Speculation 309
6.4 Instruction Dispatching 311
6.4.1 Instruction Buffer 311
6.4.2 Dispatch Stalls 311
6.4.3 Dispatch Effectiveness 313
6.5 Instruction Execution 316
6.5.1 Issue Stalls 316
6.5.2 Execution Parallelism 317
6.5.3 Execution Latency 317
6.6 Instruction Completion 318
6.6.1 Completion Parallelism 318
6.6.2 Cache Effects 318
6.7 Conclusions and Observations 320
6.8 Bridging to the IBM POWER3 and POWER4 > 322
6.9 Summary 324
7 Intel's P6 Microarchitecture 329
7.1 Introduction 330
7.1.1 Basics of the P6 Microarchitecture 332
7.2 Pipelining 334
7.2.1 In-Order Front-End Pipeline 334
7.2.2 Out-of-Order Core Pipeline 336
7.2.3 Retirement Pipeline 337
7.3 The In-Order Front End 338
7.3.1 Instruction Cache and ITLB 338
7.3.2 Branch Prediction 341
7.3.3 Instruction Decoder 343
7.3.4 Register Alias Table 346
7.3.5 Allocator 353
- 1
- 2
- 3
前往页