DE2-70-demonstrations-V10 友晶DE2-70开发板例程

DE2_70_TV_PIP ------ This demonstration will multiplex two different video source signals from the TV decoders and display both video signals on the LCD/CRT monitor with picture in picture mode (PIP mode : One picture is displayed on the full screen and the other picture is displayed in a small sub window) through the VGA port. Running the Design ------------------ 1) Connect composite video output (yellow plug) of DVD player 1 and DVD player2 to the Video-in 1 and Video-in 2 RCA jack (J8 and J9) of the DE2-70 board respectively. 2) Launch the Quartus II software. 3) Open the DE2_70_TV_PIP.qpf project located in the <install path>\DE2_70_TV_PIP folder. (File menu -> Open Project) 4) Open the Programmer window. (Tools menu -> Programmer) 5) The DE2_70_TV_PIP.sof programming file should be listed. Check the 'Program/Configure' box and set up the JTAG programming hardware connection via the 'Hardware Setup' button. 6) Press 'Start' to start programming. The design should now be programmed and running. User Inputs to the Design ------------------------- SWITCH OPERATION: SW[17:16]=01 :Video 1 OUT only SW[17:16]=00 :Video 2 OUT only SW[17:16]=11 :PIP = Video 1 (main) + Video 2 (sub) OUT SW[17:16]=10 :PIP = Video 1 (sub) + Video 2 (main) OUT Compiling the Design -------------------- 1) Launch the Quartus II software. 2) Open the DE2_70_TV_PIP.qpf project located in the <install path>\DE2_70_TV_PIP folder. (File menu -> Open Project) 3) Start compilation. (Processing -> Start Compilation) 4) After compilation is finished, you can run the design with the generated SOF file. See 'Running the Design' above. Note that here are two encrypted verilog files in the "DE2_70_TV_PIP" demonstraction. If users want to modify this demonstration and re-compile the project, please perform the following steps: 1.Use Notepad or other text edit software to open the file "Teraisc_license.dat", which is located in the "DE2_70_demonstrations/License for encrypted IP" folder of the DE2-70 System CD-ROM. 2. The license contains the FEATURE lines required to license the IP Cores as shown below FEATURE 535C_0009 alterad 9999.12 permanent uncounted D702CF471AC0 \ VENDOR_STRING="ddddddddhbilhyyyyyyyyUCIwiFFFFFFFF170M8XXXXXXXXpLsGcTTTTTTTTt7X8GAAAAAAAAbEQP0hhhhhhhhgrtJieeeeeeeebTNOVJJJJJJJJBLNGkuuuuuuuuDLxzRPPPPPPPPW01t4" \ HOSTID=ANY SIGN="0F45 927A 00F9 DBF3 3AAB D703 4F3D 2406 B374 \ 0E5C 87A1 34BA 10C6 0C08 E554 183B BD2D B79D D64E 3F98 393E \ 94FB F798 07B8 C334 C8B6 D1E4 36F5 67D5 1690" FEATURE 535C_000A alterad 9999.12 permanent uncounted F7FD875F1A28 \ VENDOR_STRING="ddddddddhbilhyyyyyyyyUCIwiFFFFFFFF170M8XXXXXXXXpLsGcTTTTTTTTt7X8GAAAAAAAAbEQP0hhhhhhhhgrtJieeeeeeeebTNOVJJJJJJJJBLNGkuuuuuuuuDLxzRPPPPPPPPW01t4" \ HOSTID=ANY SIGN="1834 5F1A 9CE6 15FD 9246 A640 66FE 918D 1091 \ A2D0 7DF8 7584 0E78 3732 1F48 0B24 3A92 870A EDAA F6F0 2145 \ 3098 5631 C5E1 4DC2 B14D C81A D30D 5518 63D0" 3.Open your Quartus II license.dat file in a text editor. 4.Copy the all the contents of the Terasic_license.dat and paste it at the end of your Quartus II license file. (Note: Do not delete any FEATURE lines from the Quartus II license file. Doing so will result in a non-usable license file.) 5.Open the "DE2_70_TV_PIP" project from Quartus II and compile this project. 6.After compilation is completed, it will generate a sof file named "DE2_70_TV_PIP_time_limited.sof" 7.Load this sof file into the FPGA and the demonstration will have at most one hour to be modified. In another words, the VGA output will be turned off after one hour. If users want to know more information about this demonstration, please contact us at support@terasic.com.