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7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide
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7 Series FPGAs and
Zynq-7000 SoC XADC Dual
12-Bit 1 MSPS
Analog-to-Digital Converter
User Guide
UG480 (v1.11) June 13, 2022
Xilinx is creating an environment where employees, customers,
and partners feel welcome and included. To that end, we’re
removing non-inclusive language from our products and related
collateral. We’ve launched an internal initiative to remove
language that could exclude people or reinforce historical biases,
including terms embedded in our software and IPs. You may still
find examples of non-inclusive language in our older products as
we work to make these changes and align with evolving industry
standards. Follow this link for more information.
XADC User Guide 3
UG480 (v1.11) June 13, 2022 www.xilinx.com
Table of Contents
Guide Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 1: Introduction and Quick Start
XADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
XADC Pinout Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Instantiating the XADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 2: Analog-to-Digital Converter
ADC Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 3: XADC Register Interface
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DRP JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Zynq-7000 SoC Processing System (PS) to XADC Dedicated Interface . . . . . . . . . . . . . . . . . . . . . . . 44
Chapter 4: XADC Operating Modes
Single Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Automatic Channel Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Sequencer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
External Multiplexer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Maximum and Minimum Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Automatic Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 5: XADC Timing
Continuous Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Event-Driven Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Dynamic Reconfiguration Port (DRP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Chapter 6: Application Guidelines
Reference Inputs (V
REFP
and V
REFN
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Analog Power Supply and Ground (V
CCADC
and GNDADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Send Feedback
XADC User Guide 4
UG480 (v1.11) June 13, 2022 www.xilinx.com
External Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PC Board Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Appendix 7: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Send Feedback
XADC User Guide 5
UG480 (v1.11) June 13, 2022 www.xilinx.com
Preface
About This Guide
Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to enable a
common design to scale across families for optimal power, performance, and cost. The Spartan®-7 family
is the lowest density with the lowest cost entry point into the 7 series portfolio. The Artix®-7 family is
optimized for highest performance-per-watt and bandwidth-per-watt for cost-sensitive, high volume
applications. The Kintex®-7 family is an innovative class of FPGAs optimized for the best
price-performance. The Virtex®-7 family is optimized for highest system performance and capacity. The
Zynq®-7000 SoC device integrates a feature-rich dual-core Arm® Cortex™-A9 based processing system
(PS) and 28 nm Xilinx programmable logic (PL) in a single device.
This guide serves as a technical reference describing the 7 series FPGAs and Zynq-7000 SoC
XADC, a dual
12-bit, 1 MSPS analog-to-digital converter with on-chip sensors. This user guide is part of an overall set of
documentation on the 7 series FPGAs and Zynq-7000 SoC devices, which is available on the Xilinx website
at
www.xilinx.com/documentation
.
Guide Contents
This manual contains these chapters:
• Chapter 1, Introduction and Quick Start
• Chapter 2, Analog-to-Digital Converter
• Chapter 3, XADC Register Interface
• Chapter 4, XADC Operating Modes
• Chapter 5, XADC Timing
• Chapter 6, Application Guidelines
• Appendix 7, Additional Resources and Legal Notices
Example design files and Tcl console examples for the Vivado® Hardware Manager can be found in the ZIP
file that accompanies this user guide.
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