PCI EXPRESS BASE SPECIFICATION, REV 1.0
4
2.3. HANDLING OF RECEIVED TLPS..........................................................................83
2.3.1. Request Handling Rules ............................................................................86
2.3.2. Completion Handling Rules......................................................................96
2.4. T
RANSACTION ORDERING ..................................................................................97
2.5. V
IRTUAL CHANNEL (VC) MECHANISM............................................................101
2.5.1. Virtual Channel Identification (VC ID) ..................................................103
2.5.2. TC to VC Mapping ..................................................................................104
2.5.3. VC and TC Rules.....................................................................................105
2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL..........................................106
2.6.1. Flow Control Rules .................................................................................107
2.7. DATA INTEGRITY .............................................................................................115
2.7.1. ECRC Rules.............................................................................................115
2.7.2. Error Forwarding ...................................................................................119
2.8. C
OMPLETION TIMEOUT MECHANISM ...............................................................121
2.9. L
INK STATUS DEPENDENCIES...........................................................................121
2.9.1. Transaction Layer Behavior in DL_Down Status...................................121
2.9.2. Transaction Layer Behavior in DL_Up Status........................................122
3. DATA LINK LAYER SPECIFICATION ..............................................................123
3.1. DATA LINK LAYER OVERVIEW ........................................................................123
3.2. D
ATA LINK CONTROL AND MANAGEMENT STATE MACHINE...........................125
3.2.1. Data Link Control and Management State Machine Rules.....................126
3.3. FLOW CONTROL INITIALIZATION PROTOCOL....................................................127
3.3.1. Flow Control Initialization State Machine Rules....................................129
3.4. DATA LINK LAYER PACKETS (DLLPS) ............................................................132
3.4.1. Data Link Layer Packet Rules.................................................................132
3.5. DATA INTEGRITY .............................................................................................137
3.5.1. Introduction.............................................................................................137
3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter)..137
3.5.3. LCRC and Sequence Number (TLP Receiver) ........................................148
4. PHYSICAL LAYER SPECIFICATION ................................................................155
4.1. I
NTRODUCTION.................................................................................................155
4.2. L
OGICAL SUB-BLOCK.......................................................................................155
4.2.1. Symbol Encoding.....................................................................................156
4.2.2. Framing and Application of Symbols to Lanes.......................................159
4.2.3. Data Scrambling .....................................................................................162
4.2.4. Link Initialization and Training..............................................................165
4.2.5. Link Training and Status State Machine (LTSSM)..................................186
4.2.6. Link Training and Status State Descriptions...........................................189
4.2.7. Clock Tolerance Compensation ..............................................................203
4.2.8. Compliance Pattern.................................................................................204
4.3. E
LECTRICAL SUB-BLOCK.................................................................................206
4.3.1. Electrical Sub-Block Requirements.........................................................206
4.3.2. Electrical Signal Specifications ..............................................................209
4.3.3. Differential Transmitter (TX) Output Specifications ..............................214
4.3.4. Differential Receiver (RX) Input Specifications......................................218
