June 2021
JEDEC
STANDARD
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
Low Power Double Data Rate 5
(LPDDR5)
JESD209-5B
(Revision of JESD209-
5A, January 2020)
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Downloaded by Lou Church (tdntinc@comcast.net) on Oct 28, 2019, 6:39 am PDT
Downloaded by Lou Church (tdntinc@comcast.net) on Oct 28, 2019, 6:39 am PDT
JEDEC Standard No. 209-5B
i
Contents
1 Scope ........................................................................................................................ 1
2 Overview ................................................................................................................... 1
2.1 Features .................................................................................................................... 1
2.2 Functional Description ............................................................................................... 1
2.2.1 Pad Definition and Description .................................................................................. 3
2.2.2 Pin per byte ............................................................................................................... 4
2.2.3 LPDDR5/LPDDR5X Bank Architecture ...................................................................... 4
2.2.3.1 Block diagram of bank configuration and Read operation outline .............................. 5
2.2.3.1.1 4Banks / 4Bank Groups Configuration ...................................................................... 5
2.2.3.1.2 8Banks Mode Configuration (Does not apply to LPDDR5X SDRAM) ........................ 6
2.2.3.1.3 16Banks Mode Configuration .................................................................................... 7
2.2.3.2 LPDDR5/LPDDR5X Address Translation Table ......................................................... 8
2.2.3.3 Bank architecture transition ....................................................................................... 8
2.2.3.4 Burst Operation ......................................................................................................... 8
2.2.4 LPDDR5 SDRAM Addressing ...................................................................................14
2.2.5 Speed Grade ............................................................................................................20
2.2.6 Burst Sequence........................................................................................................22
3 WCK Clocking ..........................................................................................................23
4 Initialization and Training ..........................................................................................26
4.1 Power-up, Initialization and Power-off Procedure .....................................................26
4.1.1 Voltage Ramp and Device Initialization ....................................................................26
4.1.2 Dual VDD2 Rail setting (MR13 OP[7]) and its change ..............................................30
4.1.3 Reset Initialization with Stable Power .......................................................................31
4.1.4 Power-off Sequence .................................................................................................31
4.1.5 Uncontrolled Power-off Sequence ............................................................................31
4.2 Training ....................................................................................................................32
4.2.1 ZQ Calibration ..........................................................................................................32
4.2.1.1 Calibration During Powerup and Initialization ...........................................................32
4.2.1.1.1 Background Calibration ............................................................................................33
4.2.1.1.2 Latching ZQ Calibration Results in Background Calibration Mode ............................34
4.2.1.1.3 Command-Based Calibration ...................................................................................34
4.2.1.1.4 Latching ZQ Calibration Results in Command-Based Calibration Mode ...................35
4.2.1.1.5 Maintaining Accurate Calibration - Background Calibration Mode ............................35
4.2.1.1.6 Maintaining Accurate Calibration – Command-Based Calibration Mode ...................36
4.2.1.1.7 Changing between Calibration Modes ......................................................................36
4.2.1.1.7.1 Changing between Calibration Modes when DVFSQ is not active ............................36
4.2.1.1.7.2 Changing between Calibration Modes when DVFSQ is active ..................................37
4.2.1.2 ZQ Stop Functionality ...............................................................................................38
4.2.1.2.1 ZQ Resistor Sharing by Other Device(s) ..................................................................38
4.2.1.2.1.1 ZQ Resistor Sharing in Background Calibration Mode .............................................38
4.2.1.2.1.2 ZQ Resistor Sharing in Command-Based Calibration Mode .....................................
38
4
.2.1.2.2 Stopping Background Calibration when DVFSQ is active .........................................38
4.2.1.2.3 Stopping Background Calibration when VDDQ is Powered Off ................................39
4.2.1.3 ZQ Reset..................................................................................................................40
4.2.1.4 Multi-die Package Considerations ............................................................................40
4.2.1.4.1 Other Considerations in Background Calibration Mode ............................................41
4.2.1.4.2 Other Considerations in Command-Based Calibration Mode ...................................41
4.2.1.5 ZQ External Resistor, Tolerance, and Capacitive Loading ........................................41
4.2.1.6 Flow Chart Examples ...............................................................................................41
4.2.2 Command Bus Training ............................................................................................47
4.2.2.1 Three physical Mode Register ..................................................................................47
4.2.2.2 Command Bus Training Mode1 ................................................................................48
