7.4.1 Wake-up Controller .............................................................................................. 36
7.4.2 Retention I/O Function ......................................................................................... 37
7.5 Pulse Counter ..................................................................................................................... 38
7.5.1 Introduction .......................................................................................................... 38
7.5.2 Functional Description ......................................................................................... 38
7.6 HW Accelerators ................................................................................................................. 39
7.6.1 Zeroing of SRAM ................................................................................................. 39
7.6.2 CRC Calculation .................................................................................................. 39
7.6.3 Pseudo Random Number Generator (PRNG) ..................................................... 39
7.7 DMA Operation ................................................................................................................... 40
7.7.1 DMA1 ................................................................................................................... 40
7.7.2 DMA2 (Fast DMA) ............................................................................................... 42
7.8 Simple Memory Protection .................................................................................................. 43
7.9 Bus Protection of Serial Slave Interfaces ............................................................................ 44
7.10 Watchdog Timer .................................................................................................................. 44
7.11 Clock Generator .................................................................................................................. 46
8 Crypto Engine .............................................................................................................................. 47
9 Peripherals ................................................................................................................................... 48
9.1 QSPI Master with XIP Feature ............................................................................................ 48
9.2 SPI Master .......................................................................................................................... 50
9.3 SPI Slave ............................................................................................................................ 51
9.4 SDIO.................................................................................................................................... 54
9.5 I2C Interface ........................................................................................................................ 55
9.5.1 I2C Master ........................................................................................................... 55
9.5.2 I2C Slave ............................................................................................................. 57
9.6 SD/SDeMMC ....................................................................................................................... 58
9.6.1 Block Diagram ..................................................................................................... 58
9.7 I2S ....................................................................................................................................... 59
9.7.1 Block Diagram ..................................................................................................... 60
9.7.2 I2S Clock Scheme ............................................................................................... 61
9.7.3 I2S Transmit and Receive Timing Diagram ......................................................... 62
9.8 ADC (Aux 12-bit) ................................................................................................................. 64
9.8.1 Overview .............................................................................................................. 64
9.8.2 Timing Diagram ................................................................................................... 64
9.8.3 DMA Transfer ...................................................................................................... 65
9.8.4 Sensor Wake-up .................................................................................................. 65
9.8.5 ADC Ports ............................................................................................................ 65
9.9 GPIO ................................................................................................................................... 66
9.9.1 Antenna Switching Diversity ................................................................................ 66
9.10 UART ............................................................................................................................. 67
9.10.1 RS-232 ................................................................................................................. 69
9.10.2 RS-485 ................................................................................................................. 69
9.10.3 Baud Rate ............................................................................................................ 70
9.10.4 Hardware Flow Control ........................................................................................ 70
9.10.5 Interrupts .............................................................................................................. 71
9.10.6 DMA Interface ...................................................................................................... 71
9.11 PWM ............................................................................................................................. 72