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DA14531

Ultra Low Power Bluetooth 5.1 SoC

Datasheet

Revision 2.0

13-Oct-2019

CFR0011-120-00

1 of 355

General Description

The DA14531 is an ultra-low power SoC integrating a 2.4 GHz transceiver and an ARM® Cortex-

M0+

microcontroller with a RAM of 48 kB and a One-Time Programmable (OTP) memory of 32 kB.

It can be used as a standalone application processor or as a data pump in hosted systems.

The radio transceiver, the baseband processor, and the qualified Bluetooth® low energy stack is fully

compliant with the Bluetooth® Low Energy 5.1 standard.

The DA14531 has dedicated hardware for the Link Layer implementation of BLE and interface

controllers for enhanced connectivity capabilities.

The BLE firmware includes the L2CAP service layer protocols, Security Manager (SM), Attribute

Protocol (ATT), the Generic Attribute Profile (GATT), and the Generic Access Profile (GAP). All

profiles published by the Bluetooth® SIG as well as custom profiles are supported.

The device is suitable for disposables, wireless sensor nodes, beacons, proximity tags and trackers,

smart HID devices (stylus, keyboards, mice, and trackpads), toys, and medical and industrial

applications.

Key Features

■ Compatible with Bluetooth V5.1, ETSI EN 300

328 and EN 300 440 Class 2 (Europe), FCC

CFR47 Part 15 (US) and ARIB STD-T66

(Japan)

■ Supports up to three BLE connections

■ Typical cold boot to radio active 35 ms

■ Processing power

□ 16 MHz 32-bit ARM® Cortex-M0+ with

SWD interface

□ Dedicated Link Layer Processor

□ AES-128 Encryption Processor

□ Software-based certified True Random

Number Generator (TRNG)

■ Memories

□ 32 kB One-Time-Programmable (OTP)

□ 48 kB Retainable System RAM

□ 144 kB ROM

■ Power management

□ Integrated Buck/Boost DCDC converter

□ Buck: 1.8 V ≤ V

BAT_HIGH

≤ 3.3 V if OTP read

needed

□ Buck: 1.1 V ≤ V

BAT_HIGH

≤ 3.3 V if RAM

retained

□ Boost: 1.1 V ≤ V

BAT_LOW

≤ 1.65 V

□ Clock-less hibernation mode: Buck 270

nA, Boost 240 nA

□ 10-bit ADC for battery voltage monitoring

□ Built-in temperature sensor for die

temperature monitoring

■ Digital controlled oscillators

□ 32 MHz crystal and 32 MHz RC oscillator

□ 32 kHz crystal and 32/512 kHz RC

oscillator

■ 15 kHz RCX as 32 kHz crystal replacement

■ Programmable Reset Circuitry

■ 2× General purpose Timers with capture and

PWM capabilities

■ Digital interfaces

□ GPIOs: 6 (WLCSP17), 12 (FCGQFN24)

□ 2× UARTs (one with flow control)

□ SPI Master/Slave up to 32 MHz (Master)

□ I2C bus at 100 kHz and 400 kHz

□ 3-axis capable Quadrature Decoder

□ Keyboard controller

■ Analog interfaces

□ 4-channel 10-bit ADC

■ Radio transceiver

□ Fully integrated 2.4 GHz CMOS

transceiver

□ Single wire antenna

□ TX: 3.5 mA, RX: 2.2 mA (system currents

with DC-DC, V

BAT_HIGH

=3 V and 0 dBm)

□ Programmable transmit output power from

-19.5 dBm to +2.5 dBm

□ -94 dBm receiver sensitivity

■ Packages:

□ WLCSP 17 balls, 1.7 × 2.05, 0.5 mm pitch

□ FCGQFN 24 pins, 2.2 × 3, 0.4 mm pitch

DA14531

Ultra Low Power Bluetooth 5.1 SoC

Datasheet

Revision 2.0

13-Oct-2019

CFR0011-120-00

3 of 355

Contents

General Description ............................................................................................................................ 1

Key Features ........................................................................................................................................ 1

Applications ......................................................................................................................................... 2

Key Benefits ......................................................................................................................................... 2

System Diagram .................................................................................................................................. 2

Contents ............................................................................................................................................... 3

Figures .................................................................................................................................................. 8

Tables ................................................................................................................................................. 10

1 Block Diagram ............................................................................................................................. 19

2 Pinout ........................................................................................................................................... 20

2.1 DA14531 WLCSP17 Ball Assignment and Description ...................................................... 20

2.2 DA14531 FCGQFN24 Pinout .............................................................................................. 24

3 Specifications .............................................................................................................................. 29

3.1 Absolute Maximum Ratings ................................................................................................ 30

3.2 Recommended Operating Conditions ................................................................................. 31

3.3 DC Characteristics .............................................................................................................. 31

3.4 Timing Characteristics ......................................................................................................... 33

3.5 RCX Oscillator ..................................................................................................................... 33

3.6 XTAL32MHz Oscillator ........................................................................................................ 34

3.7 XTAL32kHz Oscillator ......................................................................................................... 35

3.8 RC32MHz Oscillator ............................................................................................................ 35

3.9 DC-DC Converter ................................................................................................................ 35

3.10 LDO_LOW Characteristics .................................................................................................. 37

3.11 Digital I/O Characteristics.................................................................................................... 38

3.12 Power On Reset .................................................................................................................. 39

3.13 GP ADC .............................................................................................................................. 39

3.14 Temperature Sensor ........................................................................................................... 40

3.15 Radio ................................................................................................................................... 41

4 System Overview ......................................................................................................................... 45

4.1 Internal Blocks ..................................................................................................................... 45

4.2 Power Management Unit..................................................................................................... 46

4.2.1 Introduction .......................................................................................................... 46

4.2.2 Architecture .......................................................................................................... 46

4.2.2.1 Digital Power Domains .................................................................... 48

4.2.2.2 Power Modes ................................................................................... 50

4.2.3 Programming ....................................................................................................... 53

4.2.3.1 Buck Configuration .......................................................................... 53

4.2.3.2 Boost Configuration ......................................................................... 54

4.2.3.3 Bypass Configuration....................................................................... 55

4.3 HW FSM (Power-up, Wake-up, and Go-to-Sleep) .............................................................. 55

4.3.1 Power-up/Wake-up in Buck Configuration........................................................... 56

4.3.2 Power-up/Wake-up in Boost Configuration ......................................................... 57

4.3.3 Go-to-Sleep and Refresh Bandgap ..................................................................... 58

DA14531

Ultra Low Power Bluetooth 5.1 SoC

Datasheet

Revision 2.0

13-Oct-2019

CFR0011-120-00

4 of 355

4.4 OTP Memory Layout ........................................................................................................... 59

4.4.1 OTP Header ......................................................................................................... 59

4.4.2 Configuration Script ............................................................................................. 61

4.5 BootROM Sequence ........................................................................................................... 62

5 Reset ............................................................................................................................................. 66

5.1 Introduction ......................................................................................................................... 66

5.2 Architecture ......................................................................................................................... 66

5.2.1 POR, HW, and SW Reset .................................................................................... 66

5.2.2 POR Functionality ................................................................................................ 68

5.2.2.1 POR Timer Clock ............................................................................. 68

5.2.2.2 RST Pad .......................................................................................... 68

5.2.2.3 POR from GPIO ............................................................................... 68

5.2.3 POR Timing Diagram ........................................................................................... 68

5.2.4 POR Considerations ............................................................................................ 69

5.3 Programming ....................................................................................................................... 69

6 ARM Cortex-M0+ .......................................................................................................................... 70

6.1 Introduction ......................................................................................................................... 70

6.2 Architecture ......................................................................................................................... 71

6.2.1 Interrupts .............................................................................................................. 71

6.2.2 System Timer (systick) ........................................................................................ 73

6.2.3 Wake-Up Interrupt Controller ............................................................................... 73

6.3 Programming ....................................................................................................................... 73

7 AMBA Bus .................................................................................................................................... 74

7.1 Introduction ......................................................................................................................... 74

7.2 Architecture ......................................................................................................................... 74

7.3 Programming ....................................................................................................................... 75

8 Memory Map................................................................................................................................. 76

9 Memory Controller ...................................................................................................................... 78

9.1 Introduction ......................................................................................................................... 78

9.2 Architecture ......................................................................................................................... 78

9.2.1 Arbitration ............................................................................................................ 78

10 Clock Generation ......................................................................................................................... 80

10.1 Clock Tree ........................................................................................................................... 80

10.1.1 General Clock Constraints ................................................................................... 82

10.2 Crystal Oscillators ............................................................................................................... 82

10.2.1 Frequency Control (32 MHz Crystal) ................................................................... 82

10.2.2 Automated Trimming and Settling Notification .................................................... 83

10.3 RC Oscillators ..................................................................................................................... 84

10.3.1 Frequency Calibration .......................................................................................... 85

11 OTP Controller ............................................................................................................................. 86

11.1 Introduction ......................................................................................................................... 86

11.2 Architecture ......................................................................................................................... 86

11.2.1 OTP Accessing Considerations ........................................................................... 88

11.3 Programming ....................................................................................................................... 88

12 DMA Controller ............................................................................................................................ 89

12.1 Introduction ......................................................................................................................... 89

DA14531

Ultra Low Power Bluetooth 5.1 SoC

Datasheet

Revision 2.0

13-Oct-2019

CFR0011-120-00

5 of 355

12.2 Architecture ......................................................................................................................... 89

12.2.1 DMA Peripherals .................................................................................................. 89

12.2.2 Input/Output Multiplexer....................................................................................... 90

12.2.3 DMA Channel Operation...................................................................................... 90

12.2.4 DMA Arbitration ................................................................................................... 91

12.2.5 Freezing DMA Channels...................................................................................... 92

12.3 Programming ....................................................................................................................... 92

12.3.1 Memory to Memory Transfers.............................................................................. 92

12.3.2 Peripheral to Memory Transfers .......................................................................... 92

13 I2C Interface ................................................................................................................................. 94

13.1 Introduction ......................................................................................................................... 94

13.2 Architecture ......................................................................................................................... 94

13.2.1 I2C Bus Terms ..................................................................................................... 95

13.2.1.1 Bus Transfer Terms ......................................................................... 96

13.2.2 I2C Behavior ........................................................................................................ 96

13.2.2.1 START and STOP Generation ........................................................ 96

13.2.2.2 Combined Formats .......................................................................... 97

13.2.3 I2C Protocols ....................................................................................................... 97

13.2.3.1 START and STOP Conditions ......................................................... 97

13.2.3.2 Addressing Slave Protocol .............................................................. 97

13.2.3.3 Transmitting and Receiving Protocols ............................................. 99

13.2.4 Multiple Master Arbitration ................................................................................. 100

13.2.5 Clock Synchronization ....................................................................................... 101

13.3 Programming ..................................................................................................................... 102

14 UART ........................................................................................................................................... 103

14.1 Introduction ....................................................................................................................... 103

14.2 Architecture ....................................................................................................................... 104

14.2.1 UART (RS232) Serial Protocol .......................................................................... 104

14.2.2 Clock Support .................................................................................................... 105

14.2.3 Interrupts ............................................................................................................ 105

14.2.4 Programmable THRE Interrupt .......................................................................... 106

14.2.5 Shadow Registers .............................................................................................. 108

14.2.6 Direct Test Mode ............................................................................................... 108

14.3 Programming UART Controllers ....................................................................................... 108

15 SPI Interface ............................................................................................................................... 110

15.1 Introduction ....................................................................................................................... 110

15.2 Architecture ....................................................................................................................... 111

15.2.1 SPI Timing ......................................................................................................... 111

15.2.2 Master Mode ...................................................................................................... 112

15.2.2.1 Configuration ................................................................................. 112

15.2.2.2 Read and Write .............................................................................. 112

15.2.3 Slave Mode ........................................................................................................ 113

15.2.3.1 Configuration ................................................................................. 113

15.2.3.2 Read and Write .............................................................................. 113

16 Quadrature Decoder .................................................................................................................. 114

16.1 Introduction ....................................................................................................................... 114

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