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VIA Telecom CBP5.5/5.6 CDMA Baseband Processor Data Sheet 0550-0...
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VIA Telecom CBP5.5/5.6 CDMA Baseband Processor Data Sheet 0550-0050
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VIA Telecom, Inc. Proprietary Copyright © 2008 All Rights Reserved
The information in this document is believed to be correct at the time of writing, not printing.
VIA Telecom, Inc. reserves the right at any time to change said content, circuitry and specifications.
Data Sheet
0550-0050
10-Jan-08
CBP5.5/5.6 CDMA Baseband Processor
Features
• Single-chip CDMA baseband processor
• Supports CDMA2000® 1X (Release 0)
• Backward compatible to IS-95 standards
• Supports IS-2000 Quick Paging Channel for
improved standby time
• Support for multiple CDMA band classes (Band
Class 0/US-Cellular, Band Class 1/US-PCS,
Band Class 3/JTACS, Band Class 4/Korean-
PCS); support for additional band classes can be
added upon customer request
• Supports EVRC-B Vocoder (4GV-NB)
• Special purpose logic provides signal processing,
modulation, demodulation, hardware
accelerators, and interfaces for the keypad and
display
• Integrated mixed signal circuitry for the Rx ADC,
Rx filter, Tx DAC, Tx filter, internal PLLs, voice
codec, auxiliary ADCs, auxiliary DACs, RF
control, and 32.768 kHz oscillator
• Support for VCTCXO and VCXO with a wider
acquisition frequency range
• Support for forward and reverse link data rates of
up to 153.6 kbps (CBP5.6 only) with
convolutional decoding
• Available in a 12 mm x 12 mm, 280 ball pitch
0.65 mm, ball diameter 0.30mm (a lead-free
packages is available):
• Dual supply voltage (1.8 V digital core, 3.0 V
analog and 3.0 V digital I/O)
• 3.0 V or 1.8 V external memory interface
• USB 2.0 full speed support (12 Mbps)
• Removable User Identity Module compliant with
IS-820
• 48-voice polyphonic ringer
• ARM7TDMI® Control Processor (CP) supports
the protocol stack, user interface, and hardware
interface processing
• Two TeakLite® DSPs: one DSP supports CDMA
modem processing, the second DSP supports
CDMA voice processing
CBP5.5/5.6 CDMA Baseband Processor Data Sheet 0550-0050
Page 2 of 70
VIA Telecom, Inc. Proprietary Copyright © 2008 All Rights Reserved
The information in this document is believed to be correct at the time of writing, not printing.
VIA Telecom, Inc. reserves the right at any time to change said content, circuitry and specifications.
GPIO Interface (48)
12-Bit Auxiliary ADC
UART0
USB
ARM7TDMI
Audio Codec
Display Interface
OSC
Keypad Interface
Memory Interface (Flash/
SRAM)
12 Mbps
Hands-Free Car Kit
CDMA2000® 1X
(Release 0)
PDM DAC
Two-Wire Serial
Interface
R-UIM
Rx ADC/Modem Rx
Rx I
Rx Q
Digital Audio
Interface
Voice DSP EVRC,
QCELP13,
JTAG Interface
LCD Display
32.768 kHz Crystal Oscillator
Serial Device
UIM
ICE Debugger
Battery LDO
CBP5.5/5.6
Power
Management
Keypad
GPS RF
Antenna
TCXO
Tx DAC/Modem Tx
Tx I
Tx Q
Rx/Tx Radio Control
RF SPI
6 Chip Select
16
Data
Address
23-27
RX AGC, TX AGC,
AFC, 2 Spare
Antenna
Mixed Signal and
Modem PLL
Direct Conversion RF
CDMA bands
230.4 kbps
ETS,
Test/Calibration,
Data Port
UART1
230.4 kbps
Handset Speaker
Handset Microphone
Headset Speaker
Spare
2
2
2
PDM and I2S
UART2
GPS Baseband
921.6 kbps
(8) Input
Polyphonic Ringer
Headset Speaker
5
5
2
2
2
2
AFC
On/Off
Rx PLL/Rx AGC
Control Processor
PLL
Digital Signal
Processor
PLL
USB
PLL
2
/
/
/
/
4
4
4
Bluetooth
Figure 1 – CBP5.5/5.6 Simplified Block Diagram
CBP5.5/5.6 CDMA Baseband Processor Data Sheet 0550-0050
Page 3 of 70
VIA Telecom, Inc. Proprietary Copyright © 2008 All Rights Reserved
The information in this document is believed to be correct at the time of writing, not printing.
VIA Telecom, Inc. reserves the right at any time to change said content, circuitry and specifications.
Table of Contents
Features ............................................................................2
Description ........................................................................6
Product Function and Support...........................................6
CDMA2000® 1X Support ......................................................... 6
Interface Features .................................................................... 6
Audio Processing Support ........................................................ 6
Subsystem Support .................................................................. 6
CDMA-Specific Digital Logic..................................................... 6
Other Features ......................................................................... 6
Development Tools................................................................... 6
Product Documentation ............................................................ 6
Receive and Transmit Interfaces.......................................7
Receive Analog Interface ......................................................... 7
Transmit Analog Interface ........................................................ 8
Processors ........................................................................8
Control Processor..................................................................... 8
Digital Signal Processors.......................................................... 8
External Peripheral Interfaces ...........................................8
Power On/Off, Reset, and Clock Generation Interface............. 8
Reset Interface ......................................................................... 9
Analog and Digital Audio Interface ........................................... 9
GPIO, Interrupt, and Output-Only Interfaces ............................ 9
UART Ports ............................................................................ 10
USB ........................................................................................ 10
Serial Peripheral Interface (SPI)............................................. 10
Two-Wire Serial Interface ....................................................... 10
Removable User Identity Module Interface ............................ 10
Keypad and Display Interfaces............................................... 11
Dedicated Radio Control Interface ......................................... 11
Dedicated External GPS Control Interface ............................. 12
Pulse Density Modulated Auxiliary DACs ...............................12
Auxiliary ADC ..........................................................................12
Mixed Signal Bias Circuits.......................................................12
Test and Debug Interfaces......................................................12
Development Tools ......................................................... 12
CDS.........................................................................................12
ETS .........................................................................................12
Power Off, Clock Generation, and Reset Pins ........................24
Audio Function Pins ................................................................25
External Memory Interface Pins ..............................................26
GPIO, Interrupt, and Output-Only Pins ...................................29
UARTs.....................................................................................32
USB.........................................................................................33
Analog Mixed Signal Biasing and Configuration Interface ......37
Test and Debug Interface........................................................37
Memory Map................................................................... 40
Control Processor Memory Subsystem...................................40
Memory Requirements............................................................41
Software Features and Function ..................................... 42
Additional Software Function ..................................................43
Software Architecture...................................................... 45
APIs.........................................................................................45
Software Modules Description ................................................46
Electrical Characteristics................................................. 47
Absolute Maximum Ratings ....................................................47
Recommended Operating Conditions .....................................47
DC Electrical Characteristics...................................................48
AC Timing ...............................................................................49
Typical Current Consumption.......................................... 64
Ordering Information ....................................................... 69
CBP5.5/5.6 CDMA Baseband Processor Data Sheet 0550-0050
Page 4 of 70
VIA Telecom, Inc. Proprietary Copyright © 2008 All Rights Reserved
The information in this document is believed to be correct at the time of writing, not printing.
VIA Telecom, Inc. reserves the right at any time to change said content, circuitry and specifications.
Table of Figures
Figure 1 – CBP5.5/5.6 Simplified Block Diagram 2
Figure 2 - CBP5.5/5.6 Interface Block Diagram .. 7
Figure 3 - CBP5.5/5.6 Ball Descriptions (Grouped by
Function)............................................ 14
Figure 4 – CBP5.5/5.6 High-Level Software
Architecture........................................ 45
Figure 5 – PWR_OFF Timing Diagram ............... 48
Figure 6 - AC Test Load and Waveform for Standard
Outputs .............................................. 49
Figure 7 - RESET_IN_N and RESET_OUT_N
Timing ................................................ 50
Figure 8 - External Timing Diagram for 16-Bit CP
Read and Write in Asynchronous Mode
........................................................... 51
Figure 9 - External Timing Diagram for 8-Bit Lower
Byte CP Read and Write in
Asynchronous Mode .......................... 52
Figure 10 - 32-Bit Burst Flash Read at Low Speed
........................................................... 54
Figure 11 - 16-Bit Burst Flash Read .................... 56
Figure 12. 32-Bit Burst Flash Write .................... 58
Figure 13 - External Voice Codec Timing Diagram
(Mode 3)............................................. 59
Figure 14 - Ringer Output Timing for PDM Mode 59
Figure 15 - Ringer Output Timing for I2S Mode .. 60
Figure 16 – 6x4 Keypad Interface Timeline......... 60
Figure 17 - 6x5 Keypad Interface Timeline.......... 61
Figure 18 - Backlight and Contrast PWM Timing
Diagram ............................................. 61
Figure 19 – RF SPI and General Purpose SPI
Timing Example #1 ............................ 63
Figure 20 – RF SPI and General Purpose SPI
Timing Example #2 ............................ 63
Figure 21 - PLL Unlock Detection Timing............ 64
Figure 22 – Package Outline Drawing, Top View 65
Figure 23 – Package Outline Drawing Bottom View
........................................................... 66
Figure 24 – Package Outline Drawing Side View 67
Figure 25 – Solder Reflow 220 °C Profile for Lead-
Containing Packages ......................... 67
Figure 26 – Solder Reflow 260 °C Profile for Lead-
Free Packages................................... 68
CBP5.5/5.6 CDMA Baseband Processor Data Sheet 0550-0050
Page 5 of 70
VIA Telecom, Inc. Proprietary Copyright © 2008 All Rights Reserved
The information in this document is believed to be correct at the time of writing, not printing.
VIA Telecom, Inc. reserves the right at any time to change said content, circuitry and specifications.
Table of Tables
Table 1 Signal Listing (12mm x 12mm Package,
Sorted by Ball Number) ..................... 15
Table 2 – Receive IQ Analog Interface Pins ....... 23
Table 3 – Transmit IQ Analog Interface Pins ...... 23
Table 4 – Power Off Pin ...................................... 24
Table 5 – Clock Generation Pins......................... 24
Table 6 – Reset Pins ........................................... 24
Table 7 – Microphone Path Pins ......................... 25
Table 8 – Speaker Path Pins............................... 25
Table 9 – Digital Audio Interface Pins ................. 25
Table 10 – Ringer Output Pins ............................ 26
Table 11 – Address Bus Interface Pins ............... 26
Table 12 – Data Bus Interface Pins..................... 27
Table 13 – Control Signal Pins ............................ 28
Table 14 – General Purpose Inputs/Outputs (ARM-
Related) Pins ..................................... 29
Table 15 – General Purpose Inputs/Outputs (DSP-
Related) Pins ..................................... 30
Table 16 – General Purpose Interrupt Pins......... 31
Table 17 – Grouped General Purpose Input/Output
Pins .................................................... 31
Table 18 – General Purpose Output Only (ARM-
Related) Pins ..................................... 31
Table 19 – General Purpose Output Only (DSP-
Related) Pins ..................................... 32
Table 20 – UART2 Pins....................................... 32
Table 21 – UART1 Pins....................................... 32
Table 22 – UART0 Pins....................................... 33
Table 23 – USB Pins ........................................... 33
Table 24 – RF SPI Pins ....................................... 33
Table 25 – General Purpose SPI Pins................. 34
Table 26 – Serial Interface Pins .......................... 34
Table 27 – R-UIM Pins ........................................ 34
Table 28 – Keypad Matrix Interface Pins............. 34
Table 29 – Keypad and Display Control Signal Pins
........................................................... 35
Table 30 – Dedicated Radio Control Interface Pins
........................................................... 35
Table 31 – Dedicated External GPS Subsystem
Interface Pins ..................................... 36
Table 32 – PDM Interface Pins............................ 36
Table 33 – Aux ADC Interface Pins..................... 36
Table 34 – Transmitter Pin .................................. 37
Table 35 – Audio Pin ........................................... 37
Table 36 – Bandgap Reference Pin..................... 37
Table 37 – Bias Pins............................................ 37
Table 38 – JTAG Pins.......................................... 38
Table 39 – Power Pins......................................... 38
Table 40 – Ground Pins....................................... 39
Table 41 – Other Test Pins.................................. 39
Table 42 – CP Memory Map................................ 40
Table 43 – External Memory Chip Selects .......... 41
Table 44 – CBP5.5/5.6 Software Modules Memory
Requirements..................................... 42
Table 45 – 3GPP2 Service Options Supported by
CBP5.5/5.6 Software ......................... 42
Table 46 – Proprietary Service Options Supported
by CBP5.5/5.6 Software..................... 43
Table 47 – Additional Software Features Supported
........................................................... 43
Table 48 – TCXO Accuracy and Turn On Timing 49
Table 49 – Reset Timing Parameter.................... 50
Table 50 - External Bus Timing Parameters at 30 pf
Load ................................................... 52
Table 51 – 32-Bit Burst Flash Read at Low Speed
........................................................... 55
Table 52 - 16-Bit Read From Burst Flash............ 56
Table 53 - 32-Bit Write......................................... 58
Table 54 – DAI Timing Parameters ..................... 59
Table 55 – Backlight/Contrast Timing Parameters
........................................................... 61
Table 56 – Timing Parameters for RF SPI and
General Purpose SPI ......................... 63
Table 57 – CDMA Current Consumption............. 64
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资源评论
- zhaoweicpp2014-12-26不错 可以参考
- apm19892012-09-05感觉还行吧,虽然讲的不是很细
sunriseye
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