JEDEC Publication No. 157
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RECOMMEND ESD-CDM TARGET LEVELS
Foreword
CDM has become the primary real world ESD event metric describing ESD charging and rapid discharge
events in automated handling, manufacturing and assembly of IC devices. Its importance has dramatically
increased in the last few years as package feature sizes, capacitance and pin count have scaled upward. In
recent years, arbitrary CDM protection levels have been specified as IC qualification goals with little
background information available on actual/realistic CDM event levels and the protection methods
available in controls and device design for safe production of IC components. The rapid advancement of
IC technology scaling, coupled with the increased demand for high speed circuit performance, are making
it increasingly difficult to guarantee the commonly customer specified “500V” CDM specification. At the
same time, the required static control methods available for production area CDM protection at each
process step have not been fully outlined. Therefore, a realistic CDM specification target must be defined
in terms of available and commonly practiced CDM control methods, and also must reflect current ESD
design constraints.
By balancing improved static control technology specific to CDM, and limited ESD design capability in
today’s leading technologies, we recommend a CDM specification target level of 250V. This is
considered to be a realistic and safe CDM level for manufacturing and handling of today’s products using
basic CDM control methods.
At the same time we show that the current trend of silicon technology scaling will continue to place
further restrictions on achievable CDM levels. It is therefore necessary that we present a realistic CDM
roadmap for consideration by the industry moving forward to the next two levels of scaled technologies
approaching 22nm and beyond.
Introduction
This document was written with the intent to provide information for quality organizations in both
semiconductor companies and their customers to assess and make decisions on safe ESD CDM level
requirements. We will show through this document why a more realistic definition of the ESD CDM
target levels for components is not only essential but is also urgent. The document is organized in
different clauses with additional information in the annexes to give as many technical details as possible
to support the purpose given in the abstract. Frequently Asked Questions (FAQ) are also included in
Annex F so that the reader can readily find critical information without having to scan through the whole
document. Additionally, these FAQ’s are intended to avoid any misconceptions that commonly occur
while interpreting the data and the conclusions herein. All component level ESD testing specified within
this document adheres to the methods defined in the appropriate JEDEC and ANSI/ESDA as well as
JEITA specifications.
JEDEC
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