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lecture10-140706
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Lecture 10 – MOS Capacitor Model and Large Signal Model Dependence (3/10/14) Page 10-1
CMOS Analog Circuit Design © P.E. Allen - 2016
LECTURE 10 – MOS CAPACITOR MODEL AND LARGE
SIGNAL MODEL DEPENDENCE
LECTURE ORGANIZATION
Outline
• MOSFET capacitor model
• Dependence of the large signal model on process
• Dependence of the large signal model on voltage
• Dependence of the large signal model on temperature
• MOSFET reliability
• Summary
CMOS Analog Circuit Design, 3
rd
Edition Reference
Pages 77-86 and new material
Lecture 10 – MOS Capacitor Model and Large Signal Model Dependence (3/10/14) Page 10-2
CMOS Analog Circuit Design © P.E. Allen - 2016
MOSFET CAPACITOR MODEL
Submicron Technology
Physical perspective:
MOSFET capacitors consist of:
• Depletion capacitances
• Charge storage or parallel plate capacitances
SiO
2
Bulk
Source Drain
Gate
C
BS
C
BD
C
4
C
1
C
2
C
3
Fig120-06
FOX
FOX
Lecture 10 – MOS Capacitor Model and Large Signal Model Dependence (3/10/14) Page 10-3
CMOS Analog Circuit Design © P.E. Allen - 2016
Deep Submicron Technology
Physical perspective:
MOSFET capacitors consist of:
• Depletion capacitances
• Charge storage or parallel plate capacitances
Lecture 10 – MOS Capacitor Model and Large Signal Model Dependence (3/10/14) Page 10-4
CMOS Analog Circuit Design © P.E. Allen - 2016
MOSFET Depletion Capacitors
Model:
1.) v
BS
FC·PB
C
BS
=
CJ·AS
1 -
v
BS
PB
MJ
+
CJSW·PS
1 -
v
BS
PB
MJSW
,
and
2.) v
BS
> FC·PB
C
BS
=
CJ·AS
1- FC
1+MJ
1 - (1+MJ)FC + MJ
V
BS
PB
+
CJSW·PS
1 - FC
1+MJSW
1 - (1+MJSW)FC + MJSW
V
BS
PB
SiO
2
Polysilicon gate
Bulk
A
B
C
D
E
F
G
H
Drain bottom = ABCD
Drain sidewall = ABFE + BCGF + DCGH + ADHE
Source
Drain
Fig. 120-07
where
AS = area of the source
PS = perimeter of the source
CJSW = zero bias, bulk source sidewall capacitance
MJSW = bulk-source sidewall grading coefficient
For the bulk-drain depletion capacitance replace "S" by "D" in the above.
Lecture 10 – MOS Capacitor Model and Large Signal Model Dependence (3/10/14) Page 10-5
CMOS Analog Circuit Design © P.E. Allen - 2016
SM Charge Storage (Parallel Plate) MOSFET Capacitances - C
1
, C
2
, C
3
and C
4
Overlap capacitances:
C
1
= C
3
= LD·W
eff
·C
ox
= CGSO
or
CGDO
(LD 0.015 µm for LDD structures)
Channel capacitances:
C
2
= gate-to-channel = C
ox
W
eff
·(L-2LD)
= C
ox
W
eff
·L
eff
C
4
= voltage dependent channel-
bulk/substrate capacitance
Bulk
LD
Mask
W
Oxide encroachment
Actual
L (L
eff
)
Gate
Mask L
Source-gate overlap
capacitance C
GS
(C
1
)
Drain-gate overlap
capacitance C
GD
(C
3
)
Actual
W (W
eff
)
Fig. 120-09
Source
Gate
Drain
Gate-Channel
Capacitance (C
2
)
Channel-Bulk
Capacitance (C
4
)
FOX FOX
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