GMW3122 GM WORLDWIDE ENGINEERING STANDARDS
© Copyright 2005 General Motors Corporation All Rights Reserved
Page 4 of 42 November 2005
over operating conditions and aging, e.g.,
temperature, supply voltage and age drift over
specified vehicle temperature including component
life time. This is to ensure proper operation of the
network, e.g., with respect to the CAN bus
resynchronization function.
Careful analysis of the bit time tolerance is
recommended when ceramic resonators and/or
PLL clocks are considered. The permitted
tolerance of the oscillator circuit is reduced when a
PLL clock is used for the CAN data link layer
controller. For example, the suitable oscillator
tolerance would be 0.1%, for the case where the
PLL circuit would exhibit an add-on tolerance of
0.35% (at 125 or 95.2 kbit/s: 0.4%).
When a ceramic resonator with a maximum
tolerance of 0.3% is used with a PLL, the add-on
clock tolerance of the PLL is limited to 0.15% (at
125 or 95.2 kbit/s: 0.2%) over a single bit time. At
a bus speed of 500 bit/s, this is equivalent to
0.15% of 2 µs, or 3 ns maximum jitter over 2 µs. At
a bus speed of 125 kbit/s, this is equivalent to
0.2% of 8 µs, or 16 ns max jitter over 8 µs. At a
bus speed of 95.2 kbit/s, this is equivalent to 0.2%
of 10.5 µs, or 21 ns max jitter over 10.5 µs.
3.3 Wake Up Techniques. Dual wire CAN allows
three types of ECU awake/sleep techniques. If a
wakeup technique is used then it must conform to
GMW3097GS EMC requirements.
a. Selective awake by an awake pulse. When
used, it will be possible to communicate on the
dual wire CAN network without forcing nodes
that are not needed to stay awake. For details
see section 3.3.1
b. Non-selective wakeup on presence of CAN
bus communication. When used, it will force
nodes to stay awake as long as ongoing
communication occurs. This is the
recommended concept for new designs. For
details see section 3.3.2.
Attention: this concept requires to employ CAN
transceiver products which support node wakeup
upon bus traffic, see 3.11.1.2.11.
c. Non-selective awake by a continuous high
level discrete signal, typically called
“Communication Enable”. When used, it will
force nodes to stay awake as long as the
discrete signal is at a high level (example:
Ignition signal). For details see section 3.3.3.
Usage of awake/sleep techniques are optional.
Whether and how the above approaches shall be
used is to be defined in the applicable platform-
specific data bus implementation document. Note
more than one of the above concepts can apply to
a particular ECU or network. For example, it may
be necessary in a subnet for an ECU to be present
which supports wakeup on bus traffic (technique 2)
and in addition to control the discrete wakeup line
(technique 3).
3.3.1 ECU Selective Awake Using a Wake Up
Wire. ECU selective awake is accomplished by a
dedicated wire, a wake up wire.
The wake up wire is a common wire for all ECU’s
connected on the same bus. Each ECU needs one
pin assigned for this function. The below parameter
specifications of the wake up wire concept support
connection of up to 22 ECU’s. The wake up wire
signal is an input/output interface, i.e., the ECU
can send and receive the wake up signal on the
same wire.
3.3.1.1 Concept Description.
3.3.1.1.1 The wake up output requirements are:
3.3.1.1.1.1 The wake up voltage V
twu
shall be
applied on the wake up wire for a time t
twuo
.
3.3.1.1.1.2 Wake up is generated as a hardware
signal on the wake up wire. The ECU generating
this signal shall wake up or notify all ECU’s
connected on the same bus.
3.3.1.1.2 The wake up input requirements are:
3.3.1.1.2.1 An ECU currently in sleep mode, that
detects a voltage in excess of Vrwu for a time
longer than trwui applied on the wake up wire, shall
switch to active mode.
3.3.1.1.2.2 The wake up pulse shall also affect an
ECU in active mode, not only an ECU that is in
sleep mode, i.e., an ECU that is in active mode
shall be able to detect the wake up pulse.
3.3.1.1.2.3 Each ECU shall be able to generate
wake up pulses and detect wake up pulses on the
wake up wire.
3.3.1.2 Wake Up Wire Basic Requirements.
3.3.1.2.1 An ECU should not change power modes
when subjected to GMW3097GS EMC conditions.
For example, the ECU shall not take
conducted/coupled immunity test conditions as
valid wake up or go to sleep events.
3.3.1.2.2 Fault tolerant modes:
3.3.1.2.2.1 ECU power loss. An ECU shall not
interfere with wake up function among other ECUs
during a loss of power or low supply voltage
condition. Upon return of power, normal wake up
operation shall resume without any operator
intervention within a time period being specified by
the ECU Component Technical Specification. If a
time period is not specified in the CTS, then the
ECU shall resume operation within t ≤ trsm. (See
Section 3.10).
Reproduced by IHS under license with GMW
Licensee=Panasonic Automotive Systems Co of America/5946710001
Not for Resale, 01/27/2006 09:11:17 MST
No reproduction or networking permitted without license from IHS
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