DRV8837, DRV8838
ZHCSA67C –JUNE 2012–REVISED FEBRUARY 2014
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)(2)
MIN MAX UNIT
Motor power supply voltage range (VM) –0.3 12 V
Logic power supply voltage range (VCC) –0.3 7 V
Control pin voltage range (IN1, IN2, PH, EN, nSLEEP) –0.5 7 V
Peak drive current (OUT1, OUT2) Internally limited A
T
J
, operating virtual junction temperature range –40 150 ºC
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 Handling Ratings
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
T
stg
Storage temperature range –60 150 ºC
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
VM Motor power supply voltage range 0 11 V
VCC Logic power supply voltage range 1.8 7 V
I
OUT
Motor peak current 0 1.8 A
f
PWM
Externally applied PWM frequency 0 250 kHz
V
LOGIC
Logic level input voltage 0 5.5 V
T
A
Operating ambient temperature –40 85 °C
(1) Power dissipation and thermal limits must be observed.
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
DRV8837, DRV8838
THERMAL METRIC
(1)
UNIT
WSON (8 TERMINALS)
Θ
JA
Junction-to-ambient thermal resistance
(2)
60.9
Θ
JC(TOP)
Junction-to-case (top) thermal resistance
(3)
71.4
Θ
JB
Junction-to-board thermal resistance
(4)
32.2
°C/W
Ψ
JT
Junction-to-top characterization parameter
(5)
1.6
Ψ
JB
Junction-to-board characterization parameter
(6)
32.8
Θ
JC(BOTTOM)
Junction-to-case (bottom) thermal resistance
(7)
9.8
(1) For more information about traditional and new thermal limits, see the IC Package Thermal Metrics Report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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