DRV8848双路H桥电机驱动器datasheet

DRV8848

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PWM

nFAULT

4 to 18 V

Controller

DRV8848

Dual

H-Bridge

Motor

Driver

1 A

VREF

PWM

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DRV8848

ZHCSCX5 –OCTOBER 2014

DRV8848 双双路路 H 桥桥电电机机驱驱动动器器

1 特特性性 3 说说明明

• 双路 H 桥电机驱动器

DRV8848 为家用电器和其它机电一体化应用提供了一

款双路 H 桥电机驱动器。该器件可用于驱动一个或两

– 单通道/双通道刷式直流

个直流电机、一个双极性步进电机或其它负载。利用

– 步进

一个简单的 PWM 接口便可轻松连接到控制器电路。

• 脉宽调制 (PWM) 控制接口

• 可选电流调节，具有 20μs 固定关断时间

每个 H 桥驱动器的输出块都包含配置为全 H 桥的 N 通

• 每个 H 桥均提供高输出电流

道和 P 通道功率 MOSFET，用于驱动电机绕组。每

– 最大驱动器电流为 2A（12V 且

个 H 桥都含有一个调节电路，可通过固定关断时间斩

= 25°C 时）

波方案调节绕组电流。 DRV8848 能够从每个输出驱动

– 并联模式下最大驱动器电流为 4A（12V 且

高达 2A 电流，在并联模式下驱动高达 4A 电流（正常

= 25°C 时）

散热，12V 且 T

= 25°C 时）。

• 工作电源电压范围为 4V 至 18V

低功耗睡眠模式可将部分内部电路关断，从而实现极低

• 3µA 低电流睡眠模式

的静态电流和功耗。这种睡眠模式可通过专用的

• 散热增强型表面贴装封装

nSLEEP 引脚来设定。

• 保护特性

– VM 欠压闭锁 (UVLO)

还提供用于 UVLO、OCP、短路保护和过热保护的内

– 过流保护 (OCP)

部保护功能。故障条件通过 nFAULT 引脚指示。

– 热关断 (TSD)

器器件件信信息息

(1)

– 故障条件指示引脚 (nFAULT)

部部件件号号封封装装封封装装尺尺寸寸（（标标称称值值））

DRV8848 HTSSOP (16) 5.00mm x 6.40mm

2 应应用用

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

• 电器

• 通用刷式电机和步进电机

• 打印机

4 简简化化电电路路原原理理图图

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLLSEL7

DRV8848

ZHCSCX5 –OCTOBER 2014

www.ti.com.cn

目目录录

8.2 Functional Block Diagram ......................................... 9

1 特特性性.......................................................................... 1

8.3 Feature Description................................................... 9

2 应应用用.......................................................................... 1

8.4 Device Functional Modes........................................ 15

3 说说明明.......................................................................... 1

9 Application and Implementation ........................ 16

4 简简化化电电路路原原理理图图........................................................ 1

9.1 Application Information............................................ 16

5 修修订订历历史史记记录录 ........................................................... 2

9.2 Typical Application ................................................. 16

6 Pin Configuration and Functions......................... 3

10 Power Supply Recommendations ..................... 18

7 Specifications......................................................... 4

10.1 Bulk Capacitance Sizing ....................................... 18

7.1 Absolute Maximum Ratings ...................................... 4

11 Layout................................................................... 19

7.2 Handling Ratings....................................................... 4

11.1 Layout Guidelines ................................................. 19

7.3 Recommended Operating Conditions....................... 4

11.2 Layout Example .................................................... 19

7.4 Thermal Information.................................................. 4

12 器器件件和和文文档档支支持持 ..................................................... 20

7.5 Electrical Characteristics........................................... 5

12.1 商标 ....................................................................... 20

7.6 Timing Requirements................................................ 6

12.2 静电放电警告......................................................... 20

7.7 Typical Characteristics.............................................. 7

12.3 术语表 ................................................................... 20

8 Detailed Description .............................................. 8

13 机机械械封封装装和和可可订订购购信信息息 .......................................... 20

8.1 Overview ................................................................... 8

5 修修订订历历史史记记录录

日日期期修修订订版版本本注注释释

2014 年 10 月 * 最初发布。

GND

(PPAD)

AIN1

AIN2

VINT

GND

VREF

BIN2

BIN1

BOUT1

nFAULT

BOUT2

BISEN

AISEN

AOUT2

AOUT1

nSLEEP

DRV8848

www.ti.com.cn

ZHCSCX5 –OCTOBER 2014

6 Pin Configuration and Functions

HTSSOP - PWP Package

16 Pins

Top View

Pin Functions

TYPE DESCRIPTION

NAME NO.

AIN1 16 I Bridge A input 1 Controls AOUT1; tri-level input

AIN2 15 I Bridge A input 2 Controls AOUT2; tri-level input

AISEN 3 O Winding A sense Connect to current sense resistor for bridge A, or GND if current regulation is not required

AOUT1 2

O Winding A output

AOUT2 4

BIN1 9 I Bridge B input 1 Controls BOUT1; internal pulldown

BIN2 10 I Bridge B input 2 Controls BOUT2; internal pulldown

BISEN 6 O Winding B sense Connect to current sense resistor for bridge A, or GND if current regulation is not required

BOUT1 7

O Winding B output

BOUT2 5

GND PWR Device ground Both the GND pin and device PowerPAD must be connected to ground

PPAD

nFAULT 8 OD Fault indication pin Pulled logic low with fault condition; open-drain output requires external pullup

nSLEEP 1 I Sleep mode input Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown

VINT 14 — Internal regulator Internal supply voltage; bypass to GND with 2.2-μF, 6.3-V capacitor

Connect to motor power supply; bypass to GND with a 0.1- and 10-μF (minimum) ceramic

VM 12 PWR Power supply

capacitor rated for VM

Full-scale current Voltage on this pin sets the full scale chopping current; short to VINT if not supplying an

VREF 11 I

reference input external reference voltage

External Components

COMPONENT PIN 1 PIN 2 RECOMMENDED

VM GND 10-µF (minimum) ceramic capacitor rated for VM

VM GND 0.1-µF ceramic capacitor rated for VM

VINT

VINT GND 6.3-V, 2.2-µF ceramic capacitor

nFAULT

VCC

(1)

nFAULT >1 kΩ

AISEN

AISEN GND Sense resistor, see Typical Application for sizing

BISEN

BISEN GND Sense resistor, see Typical Application for sizing

(1) VCC is not a pin on the DRV8848, but a VCC supply voltage pullup is required for open-drain output nFAULT; nFAULT may be pulled

up to VINT

DRV8848

ZHCSCX5 –OCTOBER 2014

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range referenced with respect to GND (unless otherwise noted)

(1)

MIN MAX UNIT

Power supply voltage (VM) –0.3 20 V

Power supply voltage ramp rate (VM) 0 2 V/µs

Internal regulator voltage (VINT) –0.3 3.6 V

Analog input pin voltage (VREF) –0.3 3.6 V

Control pin voltage (AIN1, AIN2, BIN1, BIN2, nSLEEP, nFAULT) –0.3 7 V

Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2) –0.3 VM + 0.6 V

Continuous shunt amplifier input pin voltage (AISEN, BISEN)

(2)

–0.6 0.6 V

Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2, AISEN, BISEN) Internally limited A

Operating junction temperature –40 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Transients of ± 1 V for less than 25 ns are acceptable.

7.2 Handling Ratings

MIN MAX UNIT

stg

Storage temperature range –65 150 °C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

(1)

–4 4

Electrostatic

(ESD)

discharge

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins

(2)

–1.5 1.5

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN MAX UNIT

Power supply voltage range

(1)

4 18 V

VREF

Reference rms voltage range

(2)

1 3.3 V

PWM

Applied STEP signal 0 250 kHz

VINT

VINT external load current 1 mA

rms

Motor rms current per H-bridge

(3)

0 1 A

Operating ambient temperature –40 85 °C

(1) Note that R

DS(ON)

increases and maximum output current is reduced at VM supply voltages below 5 V.

(2) Operational at VREF between 0 and 1 V, but accuracy is degraded.

(3) Power dissipation and thermal limits must be observed.

7.4 Thermal Information

THERMAL METRIC

(1)

PWP UNIT

θJA

Junction-to-ambient thermal resistance 40.3

θJC(top)

Junction-to-case (top) thermal resistance 32.7

θJB

Junction-to-board thermal resistance 28.7

°C/W

Junction-to-top characterization parameter 0.6

Junction-to-board characterization parameter 11.4

θJC(bot)

Junction-to-case (bottom) thermal resistance 4.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

DRV8848

www.ti.com.cn

ZHCSCX5 –OCTOBER 2014

7.5 Electrical Characteristics

= 25°C, over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POWER SUPPLIES (VM, VINT)

VM operating voltage 4 18 V

= 12 V, excluding winding current,

VM operating supply current 2.5 3.8 5.5 mA

nSLEEP = 1

VMQ

VM sleep mode supply current V

= 12 V, nSLEEP = 0 0.5 1.2 3 μA

SLEEP

Sleep time nSLEEP = 0 to sleep mode 1 ms

WAKE

Wake time nSLEEP = 1 to output transition 1 ms

Power-on time V

> V

UVLO

rising to output transition 1 ms

INT

VINT voltage V

> 4 V, I

OUT

= 0 A to 1 mA 3.13 3.3 3.47 V

LOGIC-LEVEL INPUTS (BIN1, BIN2, NSLEEP)

Input logic low voltage 0 0.7 V

Input logic high voltage 1.6 5.5 V

HYS

Input logic hysteresis 100 mV

Input logic low current V

= 0 V –1 1 μA

Input logic high current V

= 5 V 1 30 μA

BIN1, BIN2 200

Pulldown resistance kΩ

nSLEEP 500

AIN1 or AIN2 400 ns

DEG

Input deglitch time

BIN1 or BIN2 200 ns

AIN1 or AIN2 edge to output change 800 ns

PROP

Propagation delay

BIN1 or BIN2 edge to output change 400 ns

TRI-LEVEL INPUTS (AIN1, AIN2)

Tri-level input logic low voltage 0 0.7 V

Tri-level input Hi-Z voltage 1.1 V

Tri-level input logic high voltage 1.6 5.5 V

HYS

Tri-level input hysteresis 100 mV

Tri-level input logic low current V

= 0 V –30 –1 μA

Tri-level input logic high current V

= 5 V 1 30 μA

Tri-level pulldown resistance To GND 170 kΩ

Tri-level pullup resistance To VINT 340 kΩ

CONTROL OUTPUTS (NFAULT)

Output logic low voltage I

= 5 mA 0.5 V

Output logic high leakage V

= 3.3 V –1 1 μA

MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)

= 12 V, I = 0.5 A, T

= 25°C 550

DS(ON)

High-side FET on resistance Ω

= 12 V, I = 0.5 A, T

= 85°C

(1)

660

= 12 V, I = 0.5 A, T

= 25°C 350

DS(ON)

Low-side FET on resistance Ω

= 12 V, I = 0.5 A, T

= 85°C

(1)

420

OFF

Off-state leakage current V

= 5 V, T

= 25°C –1 1 μA

RISE

Output rise time 60 ns

FALL

Output fall time 60 ns

DEAD

Output dead time Internal dead time 200 ns

PWM CURRENT CONTROL (VREF, AISEN, BISEN)

Externally applied VREF input

REF

VREF

= 1 to 3.3 V 1 μA

current

TRIP

xISEN trip voltage For 100% current step with V

VREF

= 3.3 V 500 mV

(1) Not tested in production; limits are based on characterization data

剩余26页未读，继续阅读

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