DRV8701中文手册datasheet_DRV8701E资源-CSDN文库

中文手册

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5.9V to 45 V

DRV8701

H-Bridge Gate

Driver

VREF

PH/EN or PWM

Controller

Gate

drive

sense

sense output

nSLEEP

Shunt Amp

Protection

FETs

nFAULT

LDO

3.3 & 4.8 V

30 mA

High-side

Low-side

High-side

gate drive

current

Low-side

gate drive

current

DRIVE

DRIVE,SRC

DRIVE,SNK

STRONG

HOLD

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

DRV8701

ZHCSDO0A –MARCH 2015–REVISED MAY 2015

DRV8701 有有刷刷直直流流电电机机全全桥桥栅栅极极驱驱动动器器

1 特特性性 2 应应用用

• 单路 H 桥栅极驱动器

• 工业有刷直流电机

• 机器人

– 驱动 4 个外部 N 通道金属氧化物半导体场效应

晶体管 (MOSFET)

• 家庭自动化

– 支持 100% 脉宽调制 (PWM) 占空比

• 工业泵和阀

• 5.9V 至 45V 工作电源电压范围

• 电动工具

• 两个控制接口选项

• 手持式真空吸尘器

– PH/EN (DRV8701E)

3 说说明明

– PWM (DRV8701P)

DRV8701 是一款采用 4 个外部 N 通道 MOSFET 的单

• 可调节栅极驱动（5 级）

路 H 桥栅极驱动器，主要用于驱动 12V 至 24V 双向

– 6mA 至 150mA 拉电流

有刷直流电机。

– 12.5mA 至 300mA 灌点流

• 支持 1.8V、3.3V 和 5V 逻辑输入

该器件可通过 PH/EN (DRV8701E) 或 PWM

• 分流放大器 (20V/V)

(DRV8701P) 接口轻松连接控制器电路。内置的感测

• 集成 PWM 电流调节功能

放大器能够实现可调节的电流控制。这款栅极驱动器

– 限制电机浪涌电流

内置有相应的电路，以便能够采用固定关断时间的

• 低功耗睡眠模式 (9μA)

PWM 电流斩波来调节绕组电流。

• 两个低压降 (LDO) 稳压器，用于为外部元件供电

DRV8701 采用 9.5V V

栅极驱动电压来驱动高侧和

– AVDD：4.8V，最高支持 30mA 输出负载

低侧 FET。所有外部 FET 的栅极驱动电流均可通过

– DVDD：3.3V，最高支持 30mA 输出负载

IDRIVE 引脚上的单个外部电阻进行配置。

• 小型封装尺寸

低功耗睡眠模式可将内部电路关断，从而实现极低的静

– 24 引脚超薄型四方扁平无引线 (VQFN)

(PowerPAD™)

态电流消耗。这种睡眠模式可通过将 nSLEEP 引脚置

– 4.0mm × 4.0mm × 0.9mm

为低电平来设定。

• 保护特性：

该器件内置以下保护功能：欠压锁定、电荷泵故障、过

– VM 欠压闭锁 (UVLO)

流关断、短路保护、前置驱动器故障以及过热保护。

– 电荷泵电压 (CPUV)

故障情况通过 nFAULT 引脚指示。

– 过流保护 (OCP)

器器件件信信息息

(1)

– 前置驱动器故障 (PDF)

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

– 热关断 (TSD)

4.00mm × 4.00mm ×

– 故障状态输出 (nFAULT)

DRV8701 VQFN (24)

0.90mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

栅栅极极驱驱动动电电流流

空白

简简化化的的系系统统框框图图

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSCX5

DRV8701

ZHCSDO0A –MARCH 2015–REVISED MAY 2015

www.ti.com.cn

目目录录

7.4 Device Functional Modes........................................ 26

1 特特性性.......................................................................... 1

8 Application and Implementation ........................ 28

2 应应用用.......................................................................... 1

8.1 Application Information............................................ 28

3 说说明明.......................................................................... 1

8.2 Typical Applications ............................................... 28

4 修修订订历历史史记记录录 ........................................................... 2

9 Power Supply Recommendations...................... 32

5 Pin Configuration and Functions......................... 3

9.1 Bulk Capacitance Sizing ......................................... 32

6 Specifications......................................................... 5

10 Layout................................................................... 33

6.1 Absolute Maximum Ratings ...................................... 5

10.1 Layout Guidelines ................................................. 33

6.2 ESD Ratings.............................................................. 5

10.2 Layout Example .................................................... 33

6.3 Recommended Operating Conditions....................... 5

11 器器件件和和文文档档支支持持 ..................................................... 34

6.4 Thermal Information.................................................. 6

11.1 文档支持................................................................ 34

6.5 Electrical Characteristics........................................... 7

11.2 社区资源................................................................ 34

6.6 Typical Characteristics.............................................. 9

11.3 商标 ....................................................................... 34

7 Detailed Description ............................................ 12

11.4 静电放电警告......................................................... 34

7.1 Overview ................................................................. 12

11.5 术语表 ................................................................... 34

7.2 Functional Block Diagram ....................................... 13

12 机机械械、、封封装装和和可可订订购购信信息息....................................... 34

7.3 Feature Description................................................. 14

4 修修订订历历史史记记录录

Changes from Original (March 2015) to Revision A Page

• 已将器件状态更新为量产数据 ................................................................................................................................................. 1

DRV8701

ZHCSDO0A –MARCH 2015–REVISED MAY 2015

www.ti.com.cn

Common Pins (continued)

TYPE DESCRIPTION

NAME NO.

Controls the current regulation; apply a voltage between 0.3 V and

VREF 6 Input Analog reference input

AVDD

Open Pulled logic low with fault condition; open-drain output requires an

nFAULT 9 Fault indication pin

Drain external pullup

Open Pulled logic low when the drive current hits the current chopping

SNSOUT 10 Sense comparator output

Drain threshold; open-drain output requires an external pullup

Voltage on this pin is equal to the SP voltage times A

plus an

SO 11 Output Shunt amplifier output

offset; place no more than 1 nF of capacitance on this pin

SN 20 Input Shunt amplifier negative input Connect to SP through current sense resistor and to GND

Connect to low-side FET source and to SN through current sense

SP 21 Input Shunt amplifier positive input

resistor

GH1 17

Output High-side gate Connect to high-side FET gate

GH2 24

GL1 19

Output Low-side gate Connect to low-side FET gate

GL2 22

SH1 18

Input Phase node Connect to high-side FET source and low-side FET drain

SH2 23

External Passive Components

COMPONENT PIN 1 PIN 2 RECOMMENDED

VM1

VM GND 0.1-µF ceramic capacitor rated for VM

VM2

VM GND ≥10-µF capacitor rated for VM

VCP

VCP VM 16-V, 1-µF ceramic capacitor

CPH CPL 0.1-µF X7R capacitor rated for VM

DVDD

DVDD GND 6.3-V, 1-µF ceramic capacitor

AVDD

AVDD GND 6.3-V, 1-µF ceramic capacitor

IDRIVE

IDRIVE GND See Typical Applications for resistor sizing

nFAULT

VCC

(1)

nFAULT ≥10-kΩ pullup

SNSOUT

VCC

(1)

SNSOUT ≥10-kΩ pullup

SENSE

SP SN/GND Optional low-side sense resistor

(1) VCC is not a pin on the DRV8701, but a VCC supply voltage pullup is required for open-drain outputs nFAULT and SNSOUT. The

system controller supply can be used for this pullup voltage, or these pins can be pulled up to either AVDD or DVDD.

External FETs

Component Gate Drain Source Recommended

HS1

GH1 VM SH1

LS1

GL1 SH1 SP or GND

Supports up to 200-nC FETs at 40-kHz PWM; see

Detailed Design Procedure for more details

HS2

GH2 VM SH2

LS2

GL2 SH2 SP or GND

DRV8701

www.ti.com.cn

ZHCSDO0A –MARCH 2015–REVISED MAY 2015

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range referenced with respect to GND (unless otherwise noted)

(1)

MIN MAX UNIT

Power supply voltage (VM) –0.3 47 V

Power supply voltage ramp rate (VM) 0 2 V/µs

Charge pump voltage (VCP, CPH) –0.3 VM + 12 V

Charge pump negative switching pin (CPL) –0.3 VM V

Internal logic regulator voltage (DVDD) –0.3 3.8 V

Internal analog regulator voltage (AVDD) –0.3 5.75 V

Control pin voltage (PH, EN, IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE, SNSOUT) –0.3 5.75 V

High-side gate pin voltage (GH1, GH2) –0.3 VM + 12 V

Continuous phase node pin voltage (SH1, SH2) –1.2 VM + 1.2 V

Pulsed 10 µs phase node pin voltage (SH1, SH2) –2.0 VM + 2 V

Low-side gate pin voltage (GL1, GL2) –0.3 12 V

Continuous shunt amplifier input pin voltage (SP, SN) –0.5 1 V

Pulsed 10-µs shunt amplifier input pin voltage (SP, SN) –1 1 V

Shunt amplifier output pin voltage (SO) –0.3 5.75 V

Open-drain output current (nFAULT, SNSOUT) 0 10 mA

Gate pin source current (GH1, GL1, GH2, GL2) 0 250 mA

Gate pin sink current (GH1, GL1, GH2, GL2) 0 500 mA

Shunt amplifier output pin current (SO) 0 5 mA

Operating junction temperature, T

–40 150 °C

Storage temperature, T

stg

–65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT

Human body model (HBM) ESD stress voltage

(1)

±2000

(ESD)

Electrostatic discharge V

Charged device model (CDM) ESD stress voltage

(2)

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

VM Power supply voltage range 5.9 45 V

VCC Logic level input voltage 0 5.5 V

VREF Reference RMS voltage range (VREF) 0.3

(1)

AVDD V

PWM

Applied PWM signal (PH/EN or IN1/IN2) 100 kHz

AVDD

AVDD external load current 30

(2)

DVDD

DVDD external load current 30

(2)

Shunt amplifier output current loading (SO) 5 mA

Operating ambient temperature –40 125 °C

(1) Operational at VREF = 0 to 0.3 V, but accuracy is degraded

(2) Power dissipation and thermal limits must be observed

剩余43页未读，继续阅读

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陈熙昊

2023-07-27

手册中的图文结合清晰明了，让人能够轻松理解并操作DRV8701。

DRV8701中文手册 datasheet

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DRV8701中文手册 datasheet

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