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Liam Devlin is with Plextek Communications Technology Consultants, London Road, Great Chesterford, Essex,

CB10 1NY Tel: +44 (0)1799 533200 Fax: +44 (0)1799 533201 Email: lmd@plextek.co.uk

The Design of Integrated Switches and Phase Shifters

Liam Devlin

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∗∗

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Abstract

Integrated analogue switches can easily be designed using any Field Effect Transistor (FET) based process

[1]. The challenges in switch design tend to come in extending the upper operating frequency and/or

increasing the power handling capability. The first part of this paper describes the operation of FETs as

switches and presents design techniques for realising integrated RF and microwave switches. Consideration is

also given to techniques for improving the power handling capability of switch designs.

Phase shifting circuits allow control of the

insertion phase of a network. They find

applications in electronic beam-forming,

channel matching networks and measurement

systems. The second part of this paper details

phase shifting techniques suitable for

integrated realisations. Analogue and digitally

controlled techniques are included and

examples of phase shifter designs are

presented.

Switch Design - Introduction

The FET’s suitability for switch realisation stems

from the fact that its drain-source resistance

behaves as a voltage variable resistor, the resistance

being set by the gate-source voltage. When used as

a switch, a FET is operated with the drain and

source at zero volts DC. The RF signal path is drain

to source and the gate is the control terminal. Figure 1 shows the typical I-V characteristics of a depletion mode FET

about the Vds=0V point, for different (negative) Vgs bias voltages.

It can be seen that, in the region of

Vds=0V, the Vds/Ids characteristic

approximates a resistance (Ids ∝ Vds). For

Vgs=0V this is a low resistance (the FET is

on) and for Vgs below pinch-off, the FET is

off and presents a high resistance. This

gives rise to the simple approximate

equivalent circuit, shown in Figure 2. The

gate resistor (Rg) is included as a simple

and effective means of providing extra

isolation between the signal and control

path, a value of several kΩ is typically

used. It is possible to use such a simple biasing technique because FETs draw very little gate current

(typically < 0.5mA/mm for high gate-drain voltages and decreasing for lower). The very low DC power

consumption of FET based switches is a significant advantage compared to PIN diode based switch designs.

Figure 1: DC characteristics of a FET in the region o

switch operation

ure 2: A

roximate e

uivalent circuit of a switchin

The values of the equivalent resistor and capacitor for a

switch FET (Figure 2) are dependent on the process used

and the FET size (gate length and gate width). For a

0.5µm gate length, Metal Semiconductor Field Effect

Transistor (MESFET) process, the on-case resistance will

be around 2.5Ωmm and the off-case resistance about

9kΩmm. Although also shown as variable, the

capacitance is normally only of any real significance in

the off-case when it limits the high frequency isolation

which can be achieved. For the same 0.5µm gate length

MESFET process, a value of 0.25pF/mm would be

typical. In practice, more complex models are often used

which also model the parasitic effects of the terminal

contacts.

Switch Design – Circuit Topologies

All of the switches considered here are Single Pole

Double Throw (SPDT) designs but the same techniques

can be readily adapted to other configurations. The

simplest of all FET switches uses a single series mounted FET in each arm, as depicted in Figure 3. Control

voltages V1 and V2 are complimentary (V1 being “low” when V2 is “high” and vice-versa). This topology

can offer low loss but limited isolation, which degrades further with increasing frequency. For a given

process, the choice of FET size (total gate width)

determines the switch performance, the larger the FETs

used, the lower the on-case insertion loss but the

poorer the isolation.

Figure 4 shows the simulated performance of a simple

series FET SPDT using Marconi Materials

Technology’s (MMT’s) 0.5µm gate length, MESFET

process with switch implant profile (S20). All switch

simulations presented in this paper use this process.

The circuit was analysed as a 3-port network, S31 is

the isolated path and S21 the on-path. The isolation is

good at low frequencies but quickly falls with

increasing frequency. It drops below 20dB at just above

2GHz. It is possible to improve the isolation by

decreasing the size of the switching FETs but this

causes an increase in insertion loss and degrades the

power handling capability of the switch.

Switch isolation can easily be improved without causing

excessive increases in insertion loss by incorporating

shunt mounted FETs, as shown in Figure 5. A shunt

FET is switched on (low resistance state) when the

RFout_1

RFout_2

RFin

Figure 3: SPDT using series only FETs

Figure 4: Simulated performance of series

only SPDT

RFin

RFout_1

RFout_2

Figure 5: Series/shunt SPDT

adjacent series FET is off (high resistance state) and

vice-versa.

Figure 6 is a plot of the simulated performance of a

series/shunt switch. The isolation has increased by

around 10dB compared to the simple series FET design

but the insertion loss has increased very little. It should

be noted that the simulations have assumed ideal

grounding for the shunt FETs. Very low inductance

grounding can be achieved on many GaAs processes by

the use of low inductance, through-substrate vias.

However, in order to keep processing costs down, many

switch IC manufacturers tend not to make use of through

GaAs via holes and grounding must be provided using

bond-wires. The inductance of the bond-wire will

obviously degrade the switch isolation, as will any

additional packaging parasitics. It should also be noted

that the use of shunt FETs can degrade the power

handling capability of the design, as explained later.

The two switch topologies presented above are both

reflective designs, that is the return loss of the off-arm

is low. Terminated switches can be easily realised by

including a shunt FET and resistor (Rt) at each output,

as shown in Figure 7. In the off case Rt will be

connected to the output by the shunt mounted FET.

Choosing the combined resistance of the FET and Rt

to be 50Ω provides a well matched off-case output,

this is known as a terminated switch design.

If more isolation is required, than can be provided by a

single series/shunt design, cascading pairs of

series/shunt FETs, as shown in Figure 8, can achieve

this. The extra switch isolation

is provided at the expense of

increased insertion loss.

The simulated performance of

this double series/shunt design is

shown in Figure 9. Very good

isolation is achieved all the way

up to 10GHz, however the input

return loss is degrading with

frequency and the insertion loss

is gradually increasing. As with

the single series/shunt design,

the use of bond-wires for

grounding the shunt FETs will

degrade the isolation.

Figure 6: Simulated performance of

series/shunt SPDT

RFin

RFout_1

RFout_2

Figure 7: Terminated series/shunt SPDT

RFin

RFout_1

RFout_2

Figure 8: Double series/shunt SPDT

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