STM32F103C8T6移植FreeRTOS成功案例

/****************************************************************************** * * Copyright (C) 2015 Xilinx, Inc. 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IN NO EVENT SHALL THE * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Except as contained in this notice, the name of the Xilinx shall not be used * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * ******************************************************************************/ /****************************************************************************/ /** * * @file psu_init.c * * This file is automatically generated * *****************************************************************************/ #include <xil_io.h> #include <sleep.h> #include "psu_init.h" int mask_pollOnValue(u32 add , u32 mask, u32 value ); int mask_poll(u32 add , u32 mask ); void mask_delay(u32 delay); u32 mask_read(u32 add , u32 mask ); static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned long val) { unsigned long RegVal = 0x0; RegVal = Xil_In32 (offset); RegVal &= ~(mask); RegVal |= (val & mask); Xil_Out32 (offset, RegVal); } void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) { int rdata =0; rdata = Xil_In32(addr); rdata = rdata & (~mask); rdata = rdata | (value << shift); Xil_Out32(addr,rdata); } unsigned long psu_pll_init_data() { // : RPLL INIT /*Register : RPLL_CFG @ 0XFF5E0034</p> PLL loop filter resistor control PSU_CRL_APB_RPLL_CFG_RES 0x2 PLL charge pump control PSU_CRL_APB_RPLL_CFG_CP 0x3 PLL loop filter high frequency capacitor control PSU_CRL_APB_RPLL_CFG_LFHF 0x3 Lock circuit counter setting PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x258 Lock circuit configuration settings for lock windowsize PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f Helper data. Values are to be looked up in a table from Data Sheet (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U) RegMask = (CRL_APB_RPLL_CFG_RES_MASK | CRL_APB_RPLL_CFG_CP_MASK | CRL_APB_RPLL_CFG_LFHF_MASK | CRL_APB_RPLL_CFG_LOCK_CNT_MASK | CRL_APB_RPLL_CFG_LOCK_DLY_MASK | 0 ); RegVal = ((0x00000002U << CRL_APB_RPLL_CFG_RES_SHIFT | 0x00000003U << CRL_APB_RPLL_CFG_CP_SHIFT | 0x00000003U << CRL_APB_RPLL_CFG_LFHF_SHIFT | 0x00000258U << CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT | 0x0000003FU << CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT | 0 ) & RegMask); */ PSU_Mask_Write (CRL_APB_RPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); /*############################################################################################################################ */ // : UPDATE FB_DIV /*Register : RPLL_CTRL @ 0XFF5E0030</p> Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 The integer portion of the feedback divider to the PLL PSU_CRL_APB_RPLL_CTRL_FBDIV 0x48 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 PLL Basic Control (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00014800U) RegMask = (CRL_APB_RPLL_CTRL_PRE_SRC_MASK | CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK | 0 ); RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT | 0x00000048U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT | 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT | 0 ) & RegMask); */ PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00717F00U ,0x00014800U); /*############################################################################################################################ */ // : BY PASS PLL /*Register : RPLL_CTRL @ 0XFF5E0030</p> Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) PSU_CRL_APB_RPLL_CTRL_BYPASS 1 PLL Basic Control (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK | 0 ); RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT | 0 ) & RegMask); */ PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); /*############################################################################################################################ */ // : ASSERT RESET /*Register : RPLL_CTRL @ 0XFF5E0030</p> Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. PSU_CRL_APB_RPLL_CTRL_RESET 1 PLL Basic Control (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK | 0 ); RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT | 0 ) & RegMask); */ PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); /*############################################################################################################################ */ // : DEASSERT RESET /*Register : RPLL_CTRL @ 0XFF5E0030</p> Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. PSU_CRL_APB_RPLL_CTRL_RESET 0 PLL Basic Control (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK | 0 ); RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT | 0 ) & RegMask); */ PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); /*############################################################################################################################ */ // : CHECK PLL STATUS /*Register : PLL_STATUS @ 0XFF5E0040</p> RPLL is locked PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U) */ mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000002U); /*############################################################################################################################ */ // :