vhdl按键消抖

关于vhdl的消抖程序， library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity shift is port(sin,cp:in std_logic;f:out std_logic); end shift; architecture netlist1 of shift is component dff1 port(d,cp:in std_logic;q:out std_logic); end component; signal z:std_logic_vector(0 to 4); begin z(0)<=sin; gf:for i in 0 to 3 generate u1:dff1 port map(z(i),cp,z(i+1)); end generate; f<=not(z(4) and (not z(1))and(not z(2))and(not z(3))); end netlist1; Library ieee; use ieee.std_logic_1164.all; entity dff1 is port(d,cp:in std_logic; q:out std_logic); end dff1; architecture one of dff1 is begin process(cp) begin if cp'event and cp='1'then q<=d; end if; end process; end one;