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Vivado Design Suite User
Guide
Designing with IP
UG896 (v2024.1) June 20, 2024
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of this document
AMD Adaptive Computing is creating an environment where
employees, customers, and partners feel welcome and
included. To that end, we’re removing non-inclusive
language from our products and related collateral. We’ve
launched an internal initiative to remove language that could
exclude people or reinforce historical biases, including terms
embedded in our software and IPs. You may still find
examples of non-inclusive language in our older products as
we work to make these changes and align with evolving
industry standards. Follow this link for more information.
Table of Contents
Chapter 1: IP-Centric Design Flow........................................................................ 4
Navigating Content by Design Process.................................................................................... 6
IP Terminology.............................................................................................................................7
IP Packager.................................................................................................................................. 7
IP Integrator.................................................................................................................................8
Using Revision and Source Control ..........................................................................................8
Using Encryption......................................................................................................................... 8
Chapter 2: IP Basics....................................................................................................... 9
Using IP Project Settings............................................................................................................ 9
Using the IP Catalog................................................................................................................. 18
Creating an IP Customization..................................................................................................25
Instantiating an IP.....................................................................................................................34
Understanding IP States Within a Project..............................................................................36
Managing IP Constraints..........................................................................................................37
Setting the Target Clock Period...............................................................................................41
Synthesis Options for IP........................................................................................................... 45
Simulating IP..............................................................................................................................48
Upgrading IP..............................................................................................................................52
Understanding Multi-Level IP..................................................................................................56
Working with Debug IP.............................................................................................................58
Using a Core Container............................................................................................................ 60
Chapter 3: Using Manage IP Projects................................................................ 67
Using the Manage IP Flow....................................................................................................... 67
Chapter 4: Using IP Example Designs................................................................73
Introduction .............................................................................................................................. 73
Opening an Example Design................................................................................................... 73
Examining Standalone IP ........................................................................................................ 75
Chapter 5: Using AMD IP with Third-Party Synthesis Tools..................76
UG896 (v2024.1) June 20, 2024
Designing with IP 2
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Third-Party Synthesis Flow.......................................................................................................76
Introduction............................................................................................................................... 78
Chapter 6: Tcl Commands for Common IP Operations............................79
Introduction............................................................................................................................... 79
Using IP Tcl Commands In Design Flows .............................................................................. 79
Tcl Commands for Common IP Operations........................................................................... 81
Example IP Flow Commands................................................................................................... 83
Appendix A: Determining Why IP is Locked.................................................. 87
Introduction............................................................................................................................... 88
Appendix B: IP Files and Directory Structure............................................... 92
Introduction............................................................................................................................... 92
IP-Generated Directories and Files......................................................................................... 92
Files Associated with IP............................................................................................................ 94
Using a COE File ........................................................................................................................94
Appendix C: Using the Platform Board Flow for IP....................................98
Introduction............................................................................................................................... 98
Appendix D: Editing or Overriding IP Sources............................................104
Introduction............................................................................................................................. 104
Overriding IP Constraints.......................................................................................................104
Editing IP Sources................................................................................................................... 106
Editing Subsystem IP.............................................................................................................. 108
Appendix E: Additional Resources and Legal Notices............................109
Finding Additional Documentation.......................................................................................109
Support Resources..................................................................................................................110
References................................................................................................................................110
Revision History.......................................................................................................................112
Please Read: Important Legal Notices................................................................................. 113
UG896 (v2024.1) June 20, 2024
Designing with IP 3
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Chapter 1
IP-Centric Design Flow
The AMD Vivado™ Design Suite provides an intellectual property (IP) centric design ow that
lets you add IP modules to your design from various design sources. Central to the environment
is an extensible IP catalog that contains AMD-delivered Plug-and-Play IP. The IP catalog can be
extended by adding the following:
• Modules from System Generator for DSP designs (MATLAB
®
from Simulink
®
algorithms)
• Vivado High-Level Synthesis (HLS) designs (C/C++ algorithms)
• Third-party IP
• Designs packaged as IP using the Vivado IP packager
The following gure illustrates the IP-centric design ow.
Chapter 1: IP-Centric Design Flow
UG896 (v2024.1) June 20, 2024
Designing with IP 4
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Figure 1: IP-Centric Design Flow
*SystemVerilog files must have a Verilog Wrapper.
Xilinx IP
IP Catalog
3
rd
Party IP
User IP
X14070-030917
Add Module
Example
Designs
IP Packager
RTL Source Files
VHDL, Verilog,
SystemVerilog*,
(XCI/XCIX)
Document
Files
Simulation
Model Files
(simsets)
Test
Bench
RTL IP Source Files
VHDL, Verilog,
SystemVerilog*,
(XCI/XCIX)
Block Design
(BD)
Note: In some cases, third-party providers oer IP as synthesized EDIF netlists. You can load these les into
a Vivado design using the Add Sources command.
The available methods to work with IP in a design are:
• Use the Managed IP ow to customize IP and generate output products, including a
synthesized design checkpoint (DCP) to preserve the customizaon for use in the current and
future releases. See Chapter 3: Using Manage IP Projects for more informaon.
Chapter 1: IP-Centric Design Flow
UG896 (v2024.1) June 20, 2024
Designing with IP 5
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