Version 1.0
Date: 2015-01-20
Hardware Data Sheet Section III
ET1810 / ET1811 / ET1812
Slave Controller
IP Core for Altera® FPGAs
Release 3.0.10
Section I – Technology
(Online at http://www.beckhoff.com)
Section II – Register Description
(Online at http://www.beckhoff.com)
Section III – Hardware Description
Installation, Configuration, Resource
consumption, Interface specification
DOCUMENT ORGANIZATION
III-II Slave Controller – IP Core for Altera FPGAs
DOCUMENT ORGANIZATION
The Beckhoff EtherCAT Slave Controller (ESC) documentation covers the following Beckhoff ESCs:
ET1200
ET1100
EtherCAT IP Core for Altera
®
FPGAs
EtherCAT IP Core for Xilinx
®
FPGAs
ESC20
The documentation is organized in three sections. Section I and section II are common for all Beckhoff
ESCs, Section III is specific for each ESC variant.
The latest documentation is available at the Beckhoff homepage (http://www.beckhoff.com).
Section I – Technology (All ESCs)
Section I deals with the basic EtherCAT technology. Starting with the EtherCAT protocol itself, the
frame processing inside EtherCAT slaves is described. The features and interfaces of the physical
layer with its two alternatives Ethernet and EBUS are explained afterwards. Finally, the details of the
functional units of an ESC like FMMU, SyncManager, Distributed Clocks, Slave Information Interface,
Interrupts, Watchdogs, and so on, are described.
Since Section I is common for all Beckhoff ESCs, it might describe features which are not available in
a specific ESC. Refer to the feature details overview in Section III of a specific ESC to find out which
features are available.
Section II – Register Description (All ESCs)
Section II contains detailed information about all ESC registers. This section is also common for all
Beckhoff ESCs, thus registers, register bits, or features are described which might not be available in
a specific ESC. Refer to the register overview and to the feature details overview in Section III of a
specific ESC to find out which registers and features are available.
Section III – Hardware Description (Specific ESC)
Section III is ESC specific and contains detailed information about the ESC features, implemented
registers, configuration, interfaces, pinout, usage, electrical and mechanical specification, and so on.
Especially the Process Data Interfaces (PDI) supported by the ESC are part of this section.
Additional Documentation
Application notes and utilities can also be found at the Beckhoff homepage. Pinout configuration tools
for ET1100/ET1200 are available. Additional information on EtherCAT IP Cores with latest updates
regarding design flow compatibility, FPGA device support and known issues are also available.
Trademarks
Beckhoff
®
, TwinCAT
®
, EtherCAT
®
, Safety over EtherCAT
®
, TwinSAFE
®
and XFC
®
are registered trademarks of and licensed by
Beckhoff Automation GmbH & Co. KG. Other designations used in this publication may be trademarks whose use by third
parties for their own purposes could violate the rights of the owners.
Patent Pending
The EtherCAT Technology is covered, including but not limited to the following German patent applications and patents:
DE10304637, DE102004044764, DE102005009224, DE102007017835 with corresponding applications or registrations in
various other countries.
Disclaimer
The documentation has been prepared with care. The products described are, however, constantly under development. For that
reason the documentation is not in every case checked for consistency with performance data, standards or other
characteristics. In the event that it contains technical or editorial errors, we retain the right to make alterations at any time and
without warning. No claims for the modification of products that have already been supplied may be made on the basis of the
data, diagrams and descriptions in this documentation.
Copyright
© Beckhoff Automation GmbH & Co. KG 01/2015.
The reproduction, distribution and utilization of this document as well as the communication of its contents to others without
express authorization are prohibited. Offenders will be held liable for the payment of damages. All rights reserved in the event of
the grant of a patent, utility model or design.
DOCUMENT HISTORY
Slave Controller – IP Core for Altera FPGAs III-III
DOCUMENT HISTORY
Version
Comment
1.0
Initial release EtherCAT IP Core for Altera FPGAs 3.0.10
CONTENTS
III-IV Slave Controller – IP Core for Altera FPGAs
CONTENTS
1 Overview 1
1.1 Frame processing order 2
1.2 Scope of this document 3
1.3 Scope of Delivery 3
1.4 Target FPGAs 4
1.5 Designflow requirements 4
1.6 Tested FPGA/Designflow combinations 5
1.7 Release Notes 6
1.7.1 Major differences between V2.4.x and V3.0.x 12
1.7.2 Reading IP Core version from device 12
1.8 Design flow 13
1.9 OpenCore Plus Evaluation 14
1.10 Simulation 15
2 Features and Registers 16
2.1 Features 16
2.2 Registers 19
2.3 Extended ESC Features in User RAM 22
3 IP Core Installation 26
3.1 Installation on Windows PCs 26
3.1.1 System Requirements 26
3.1.2 Installation 26
3.2 Installation on Linux PCs 27
3.2.1 System Requirements 27
3.2.2 Installation 27
3.3 Files located in the lib folder 27
3.4 License File 28
3.5 IP Core Vendor ID package 29
3.6 Integrating the EtherCAT IP Core into the Altera Designflow 30
3.6.1 Software Templates for example designs with NIOS processor 30
3.7 EtherCAT Slave Information (ESI) / XML device description for example designs 30
4 IP Core Usage 31
4.1 IP Catalog 31
4.2 Qsys 31
5 IP Core Configuration 32
5.1 Documentation 33
5.2 Parameters 34
5.2.1 Product ID tab 34
5.2.2 Physical Layer tab 35
5.2.3 Internal Functions tab 37
CONTENTS
Slave Controller – IP Core for Altera FPGAs III-V
5.2.4 Feature Details tab 39
5.2.5 Process Data Interface tab 41
6 Example Designs 49
6.1 EBV Cyclone III DBC3C40 with Digital I/O 50
6.1.1 Configuration and resource consumption 50
6.1.2 Functionality 50
6.1.3 Implementation 50
6.1.4 SII EEPROM 50
6.1.5 Downloadable configuration file 51
6.2 EBV Cyclone IV DBC4CE55 with NIOS 52
6.2.1 Configuration and resource consumption 52
6.2.2 Functionality 52
6.2.3 Implementation 52
6.2.4 SII EEPROM 53
6.2.5 Downloadable configuration file 53
6.3 Altera Cyclone IV DE2-115 with NIOS and MII 54
6.3.1 Configuration and resource consumption 54
6.3.2 Functionality 54
6.3.3 Implementation 55
6.3.4 SII EEPROM 55
6.3.5 Downloadable configuration file 55
6.4 Altera Cyclone IV DE2-115 with NIOS and RGMII 56
6.4.1 Configuration and resource consumption 56
6.4.2 Functionality 56
6.4.3 Downloadable configuration file 56
7 FPGA Resource Consumption 57
8 IP Core Signals 59
8.1 General Signals 59
8.1.1 Clock source example schematics 60
8.2 SII EEPROM Interface Signals 61
8.3 LED Signals 61
8.4 Distributed Clocks SYNC/LATCH Signals 62
8.5 Physical Layer Interface 63
8.5.1 MII Interface 64
8.5.2 RMII Interface 66
8.5.3 RGMII Interface 67
8.6 PDI Signals 70
8.6.1 General PDI Signals 70
8.6.2 Digital I/O Interface 70
8.6.3 SPI Slave Interface 71
8.6.4 Asynchronous 8/16 Bit µController Interface 71
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