################################################################################
# Vivado (TM) v2019.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA ego1 时钟及暂停计时功能
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FPGA ego1 时钟从23:59:59:59(h:min:sec:10ms)计到0:0:0:0不断循环,拨码开关P5用于暂停。
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FPGA ego1 时钟及暂停计时功能
(282个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 26KB
elaborate.bat 1KB
simulate.bat 918B
compile.bat 836B
runme.bat 229B
runme.bat 229B
runme.bat 229B
lab6_clk.bit 2.09MB
xsim_1.c 18KB
xsim.dbg 20KB
lab6_clk_routed.dcp 228KB
lab6_clk_placed.dcp 210KB
lab6_clk_opt.dcp 168KB
lab6_clk.dcp 43KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
compile.do 691B
compile.do 667B
compile.do 626B
compile.do 616B
simulate.do 311B
simulate.do 306B
simulate.do 306B
simulate.do 195B
elaborate.do 183B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 404KB
run.f 478B
run.f 462B
usage_statistics_webtalk.html 33KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 65B
xsim.ini 26KB
xsim.ini 25KB
xsimSettings.ini 1KB
webtalk.jou 822B
webtalk_3968.backup.jou 822B
vivado.jou 710B
vivado_28748.backup.jou 681B
vivado.jou 681B
vivado.jou 676B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 32KB
runme.log 26KB
runme.log 22KB
webtalk_3968.backup.log 1001B
webtalk.log 1001B
elaborate.log 572B
xsimkernel.log 329B
simulate.log 50B
xsimcrash.log 0B
xvlog.log 0B
lab6_clk.lpr 343B
xsim.mem 27KB
xsim_0.win64.obj 395KB
xsim_1.win64.obj 13KB
elab.opt 188B
vivado.pb 44KB
vivado.pb 35KB
place_design.pb 17KB
route_design.pb 15KB
opt_design.pb 11KB
init_design.pb 5KB
write_bitstream.pb 4KB
xelab.pb 968B
lab6_clk_power_summary_routed.pb 728B
lab6_clk_utilization_synth.pb 242B
clk_wiz_0_utilization_synth.pb 242B
lab6_clk_utilization_placed.pb 242B
vivado.pb 149B
lab6_clk_timing_summary_routed.pb 106B
lab6_clk_methodology_drc_routed.pb 52B
lab6_clk_route_status.pb 44B
lab6_clk_drc_routed.pb 37B
lab6_clk_drc_opted.pb 37B
lab6_clk_bus_skew_routed.pb 30B
xvlog.pb 16B
lab6_test_vlog.prj 883B
vlog.prj 241B
xsim.reloc 17KB
xil_defaultlib.rlx 2KB
xsim.rlx 794B
lab6_clk_timing_summary_routed.rpt 116KB
lab6_clk_io_placed.rpt 97KB
lab6_clk_clock_utilization_routed.rpt 15KB
lab6_clk_utilization_placed.rpt 9KB
lab6_clk_power_routed.rpt 8KB
lab6_clk_utilization_synth.rpt 7KB
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