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NAND Flash Memory

MT29F32G08CBABA, MT29F64G08C[E/F]ABA, MT29F128G08C[J/K]ABA,

MT29F256G08CUABA, MT29F32G08CBABB, MT29F32G08CBCBB,

MT29F64G08CFABB, MT29F64G08CECBB, MT29F128G08CJABB,

MT29F128G08CKCBB, MT29F256G08CUCBB

Features

•

Open NAND Flash Interface (ONFI) 2.1-compliant

•

Multiple-level cell (MLC) technology

•

Organization

–

Page size x8: 4320 bytes (4096 + 224 bytes)

–

Block size: 256 pages (1024K + 56K bytes)

–

Plane size: 2 planes x 2048 blocks per plane

–

Device size: 32Gb: 4096 blocks;

64Gb: 8192 blocks;

128Gb: 16,384 blocks;

256Gb: 32,786 blocks

•

Synchronous I/O performance

–

Up to synchronous timing mode 4

–

Clock rate: 12ns (DDR)

–

Read/write throughput per pin: 166 MT/s

•

Asynchronous I/O performance

–

Up to asynchronous timing mode 4

–

RC/

WC: 25ns (MIN)

•

Array performance

–

Read page: 50µs (MAX)

–

Program page: 900µs (TYP)

–

Erase block: 3ms (TYP)

•

Operating Voltage Range

–

: 2.7–3.6V

–

CCQ

: 1.7–1.95V, 2.7–3.6V

•

Command set: ONFI NAND Flash Protocol

•

Advanced Command Set

–

Program cache

–

Read cache sequential

–

Read cache random

–

One-time programmable (OTP) mode

–

Multi-plane commands

–

Multi-LUN operations

–

Read unique ID

–

Copyback

•

First block (block address 00h) is valid when ship-

ped from factory. For minimum required ECC, see

Error Management (page 107).

•

RESET (FFh) required as first command after power-

•

Operation status byte provides software method for

detecting

–

Operation completion

–

Pass/fail condition

–

Write-protect status

•

Data strobe (DQS) signals provide a hardware meth-

od for synchronizing data DQ in the synchronous

interface

•

Copyback operations supported within the plane

from which data is read

•

Quality and reliability

–

Data retention: 10 years

–

Endurance: 5000 PROGRAM/ERASE cycles

•

Operating temperature:

–

Commercial: 0°C to +70°C

–

Industrial (IT): –40ºC to +85ºC

•

Package

–

52-pad LGA

–

48-pin TSOP

–

100-ball BGA

Note:

1. The ONFI 2.1 specification is available at

www.onfi.org.

Micron Confidential and Proprietary

Advance

‡

32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND

Features

PDF: 09005aef836c9ded

Rev. A 08/09 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by

Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications.

Draft: 08/26/09

Contents

General Description ......................................................................................................................................... 9

Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9

Signal Assignments ......................................................................................................................................... 11

Package Dimensions ...................................................................................................................................... 14

Architecture ................................................................................................................................................... 20

Device and Array Organization ....................................................................................................................... 21

Bus Operation – Asynchronous Interface ........................................................................................................ 27

Asynchronous Enable/Standby ................................................................................................................... 27

Asynchronous Bus Idle ............................................................................................................................... 27

Asynchronous Commands .......................................................................................................................... 28

Asynchronous Addresses ............................................................................................................................ 29

Asynchronous Data Input ........................................................................................................................... 30

Asynchronous Data Output ........................................................................................................................ 31

Write Protect .............................................................................................................................................. 32

Ready/Busy# .............................................................................................................................................. 32

Bus Operation – Synchronous Interface ........................................................................................................... 37

Synchronous Enable/Standby ..................................................................................................................... 38

Synchronous Bus Idle/Driving .................................................................................................................... 38

Synchronous Commands ........................................................................................................................... 39

Synchronous Addresses .............................................................................................................................. 40

Synchronous DDR Data Input ..................................................................................................................... 41

Synchronous DDR Data Output .................................................................................................................. 42

Write Protect .............................................................................................................................................. 44

Ready/Busy# .............................................................................................................................................. 44

Device Initialization ....................................................................................................................................... 45

Activating Interfaces ....................................................................................................................................... 46

Activating the Asynchronous Interface ........................................................................................................ 46

Activating the Synchronous Interface .......................................................................................................... 46

Command Definitions .................................................................................................................................... 48

Reset Operations ............................................................................................................................................ 50

RESET (FFh) ............................................................................................................................................... 50

SYNCHRONOUS RESET (FCh) .................................................................................................................... 51

Identification Operations ................................................................................................................................ 52

READ ID (90h) ............................................................................................................................................ 52

READ ID Parameter Tables ............................................................................................................................. 53

Configuration Operations ............................................................................................................................... 54

SET FEATURES (EFh) ................................................................................................................................. 54

GET FEATURES (EEh) ................................................................................................................................. 55

READ PARAMETER PAGE (ECh) ...................................................................................................................... 59

Parameter Page Data Structure Tables ............................................................................................................. 60

READ UNIQUE ID (EDh) ................................................................................................................................ 70

Status Operations ........................................................................................................................................... 71

READ STATUS (70h) ................................................................................................................................... 72

READ STATUS ENHANCED (78h) ............................................................................................................... 73

Column Address Operations ........................................................................................................................... 74

CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 74

CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 75

CHANGE WRITE COLUMN (85h) ................................................................................................................ 76

CHANGE ROW ADDRESS (85h) ................................................................................................................... 77

Read Operations ............................................................................................................................................. 79

Micron Confidential and Proprietary

Advance

32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND

PDF: 09005aef836c9ded

Rev. A 08/09 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Draft: 08/26/09

READ MODE (00h) ..................................................................................................................................... 81

READ PAGE (00h-30h) ................................................................................................................................ 82

READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 83

READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 84

READ PAGE CACHE LAST (3Fh) .................................................................................................................. 86

READ PAGE MULTI-PLANE (00h-32h) ........................................................................................................ 87

Program Operations ....................................................................................................................................... 89

PROGRAM PAGE (80h-10h) ........................................................................................................................ 89

PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 91

PROGRAM PAGE MULTI-PLANE 80h-11h ................................................................................................... 93

Erase Operations ............................................................................................................................................ 95

ERASE BLOCK (60h-D0h) ............................................................................................................................ 95

ERASE BLOCK MULTI-PLANE (60h-D1h) .................................................................................................... 96

Copyback Operations ..................................................................................................................................... 97

COPYBACK READ (00h-35h) ....................................................................................................................... 98

COPYBACK PROGRAM (85h–10h) ............................................................................................................... 99

COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 99

COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 100

One-Time Programmable (OTP) Operations ................................................................................................... 101

PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 102

PROTECT OTP AREA (80h-10h) .................................................................................................................. 103

READ OTP PAGE (00h-30h) ........................................................................................................................ 104

Multi-Plane Operations ................................................................................................................................. 105

Multi-Plane Addressing ............................................................................................................................. 105

Interleaved Die (Multi-LUN) Operations ........................................................................................................ 106

Error Management ........................................................................................................................................ 107

Output Drive Impedance ............................................................................................................................... 108

AC Overshoot/Undershoot Specifications ...................................................................................................... 111

Input Slew Rate ............................................................................................................................................. 112

Output Slew Rate ........................................................................................................................................... 113

Electrical Specifications ................................................................................................................................. 114

Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 116

Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) .................................. 117

Electrical Specifications – DC Characteristics and Operating Conditions (V

CCQ

) ............................................... 117

Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 118

Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 119

Electrical Specifications – Array Characteristics .............................................................................................. 123

Asynchronous Interface Timing Diagrams ...................................................................................................... 124

Synchronous Interface Timing Diagrams ........................................................................................................ 135

Revision History ............................................................................................................................................ 157

Rev. E – 8/09 .............................................................................................................................................. 157

Rev. D – 2/09 ............................................................................................................................................. 157

Rev. C – 1/09 ............................................................................................................................................. 157

Rev. B – 12/08 ............................................................................................................................................ 158

Rev. A – 11/08 ............................................................................................................................................ 159

Micron Confidential and Proprietary

Advance

32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND

PDF: 09005aef836c9ded

Rev. A 08/09 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Draft: 08/26/09

List of Tables

Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9

Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 26

Table 3: Asynchronous Interface Mode Selection ........................................................................................... 27

Table 4: Synchronous Interface Mode Selection ............................................................................................. 37

Table 5: Command Set .................................................................................................................................. 48

Table 6: Read ID Parameters for Address 00h ................................................................................................. 53

Table 7: Read ID Parameters for Address 20h .................................................................................................. 53

Table 8: Feature Address Definitions .............................................................................................................. 54

Table 9: Feature Address 01h: Timing Mode ................................................................................................... 56

Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 56

Table 11: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 57

Table 12: Feature Addresses 90h: Array Operation Mode ................................................................................. 57

Table 13: Parameter Page Data Structure ....................................................................................................... 60

Table 14: Status Register Definition ............................................................................................................... 71

Table 15: OTP Area Details ........................................................................................................................... 102

Table 16: Error Management Details ............................................................................................................. 107

Table 17: Output Drive Strength Test Conditions (V

CCQ

= 1.7–1.95V) .............................................................. 108

Table 18: Output Drive Strength Impedance Values (V

CCQ

= 1.7–1.95V) .......................................................... 108

Table 19: Output Drive Strength Conditions (V

CCQ

= 2.7–3.6V) ....................................................................... 109

Table 20: Output Drive Strength Impedance Values (V

CCQ

= 2.7–3.6V) ............................................................ 109

Table 21: Pull-Up and Pull-Down Output Impedance Mismatch .................................................................... 110

Table 22: Overshoot/Undershoot Parameters ................................................................................................ 111

Table 23: Test Conditions for Input Slew Rate ................................................................................................ 112

Table 24: Input Slew Rate (V

CCQ

= 1.7–1.95V) ................................................................................................. 112

Table 25: Input Slew Rate (V

CCQ

= 2.7–3.6V) ................................................................................................... 112

Table 26: Test Conditions for Output Slew Rate ............................................................................................. 113

Table 27: Output Slew Rate (V

CCQ

= 1.7–1.95V) .............................................................................................. 113

Table 28: Output Slew Rate (V

CCQ

= 2.7–3.6V) ................................................................................................ 113

Table 29: Absolute Maximum Ratings by Device ............................................................................................ 114

Table 30: Recommended Operating Conditions ............................................................................................ 114

Table 31: Valid Blocks per LUN ..................................................................................................................... 114

Table 32: Capacitance: 100-Ball BGA Package ................................................................................................ 115

Table 33: Capacitance: 48-Pin TSOP Package ................................................................................................ 115

Table 34: Capacitance: 52-Pad LGA Package .................................................................................................. 115

Table 35: Test Conditions ............................................................................................................................. 116

Table 36: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 116

Table 37: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 117

Table 38: DC Characteristics and Operating Conditions (3.3V V

CCQ

) ............................................................... 117

Table 39: DC Characteristics and Operating Conditions (1.8V V

CCQ

) ............................................................... 118

Table 40: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 118

Table 41: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 120

Table 42: Array Characteristics ..................................................................................................................... 123

Micron Confidential and Proprietary

Advance

32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND

PDF: 09005aef836c9ded

Rev. A 08/09 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Draft: 08/26/09

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