镁光nand flash MT29F32G08CBADA MT29F32G08CBADB datesheet

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Micron Confidential and Proprietary ccr。n 32Gb, 64G Asynchronous/Synchronous NAND Features Contents Important Notes and warnings.…,…, 10 General Description........,..,..,.....,.....,,,,,,…,, Asynchronous and Synchronous Signal Descriptions Signal Assignments…….……… Package Dimensions 15 Architecture∴… 17 Device and Array organization Bus Opcration- Asynchronous Interface………………………", D看番 ·;····· 20 Asynchronous Enable/Standby ...................................................................................................................20 Asynchronous Bus Idle ....................... 20 Asynchronous Pausing Data Input/Output ∴21 Asynchronous Commands............... 21 Asynchronous Addresses............ 22 Asynchronous Data Input 23 Asynchronous Data Output ………………2 4 Write protect 25 Ready/Busy# ∴25 Bus Operation- Synchronous Interface.………, 30 Synchronous Enable/Standby ∴31 Synchronous Bus Idle/Driving 31 Synchronous Pausing Data Input/ Output………… 32 Synchronous commands…………,…,…,…,…,….,…,….,…,…,…,,…,…,…,,…,,,32 Synchronous addresses 33 Synchronous DDr data Input 34 Synchronous DDr data output…… ·非垂 35 Write protect 37 Ready/Busy#…,,,,…,…,…,…,,,…,…,,,, ···.········.··· 37 Device initialization 38 Activating Interfaces ·D垂 40 Activating the Asynchronous Interface 40 Activating the Synchronous Interface…… 看D·垂 40 Command definitions ..:·· 42 Reset operations 44 RESET 14 SYNCHIRONOUS RESET (FCh)..... 45 READ ID(90h)………………‘ RESET LUN (FAh......... Identification Operations 47 47 READ ID Parameter Tables..………,48 READ PARAMETER PAGE (ECh) 49 Parameter Pagc Data Structure Tables 5 READ UNIQUE ID(EDh).… 62 Configuration Operations…… .64 SET FEATURES(EFh)… 61 GET FEATURES(EEh)…… 看看·.音垂看垂·,垂非·垂 65 Status Operations 70 READ STATUS(70h)… 垂,·垂 71 READ STATUS ENHANCED(78h) 着垂垂·垂 72 Column Address operations 72 CHANGE READ COLUMN(O5h-EOh)............... 着番 DF:0900 3415d Micron Technology, Inc reserves the right to change products or specifications without notice. o 2012 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary ccr。n 32Gb, 64G Asynchronous/Synchronous NAND Features CHANGE READ COLUMN ENHANCED(O6h-EOh)........................ CHANGE READ COLUMN ENHANCED(O0h-05h-EOh) Operation…………,…,……,74 CHANGE WRITE COLUMN (85h) 74 CHANGE ROW ADDRESS (85h) Rcad operations,,,…,…,…,,… 非·着,垂非·看 77 READ MODE(00h)… READ PAGE (OOh-30h) 80 READ PAGE CACHE SEQUENTIAL(3lh)……,…,…,…,…,…,…,,…,…,……,81 READ PAGE CACHE RANDOM(0Oh-31h) 82 READ PAGE CACHE LAST (3Fh) 84 READ PAGE MULTI-PLANE (0Oh-32h).......... 85 Read retry operations…,…,…, 87 Program Operations……….….….….….….….….…..….….….….…..,.…..….….…...….….……..….……89 PROGRAM PAGE(80h-10h 89 PROGRAM PAGE CACHE (80h-15h)............ 91 PROGRAM PAGE MULTI-PLANE (80h-1lh) D ∴93 Erase Operations…….….….….……….…………,…….….….95 ERASE BLOCK(60h-Doh)…………………………………………,95 ERASE BLOCK MULTI-PLANE(60h-D1h 96 ERASE BLOCK MULTI-PLANE(60h-60h-DOh) 96 Copyback Operations 97 COPYBACK READ(00h-35h)……… 看·着4·垂 98 COPYBACK PROGRAM (85h-10h) 垂音,音垂垂 99 COPYBACK READ MULTI-PLANE (0Oh-32h) 99 COPYBACK PROGRAM MULTI-PLANE (85h-1lh) 看看着看,垂音D番着·垂 ·着垂D看看音垂,面垂音查 l00 One-Time Programmable (OTPOperations l00 PROGRAM OTP PAGE(80h-1Oh) LOL PROTECT OTP AREA(80h-10h).... 103 READ OTP PAGE (00h-30h) ······· 104 ulti- Plane operations∴……………… 105 Multi-Plane Addressing………………………,,… ∴105 Interleaved die( Multi-LUN) Operations…,…,…,…,…,…,…,…,…,…,……,105 Error management………… 107 Shared pages 非·看 108 Output Drive Impedance…..…,…,…,…,,,…,…,, 110 AC Overshoot/Undershoot Specifications 113 Synchronous Input Slew Rate…………………… 114 Output Slew ratc……,…,…,…,…,,, 115 Power Cycle Requirements…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,116 Electrical Specifications l17 Electrical Specifications- DC Characteristics and Operating Conditions( Asynchronous)…………….119 Electrical Specifications- DC Characteristics and Operating Conditions( Synchronous)……,…,…,……,120 Electrical Specifications- DC Characteristics and Operating Conditions(vcQ)………… 120 Electrical Specifications-AC Characteristics and Operating Conditions(Asynchronous 123 Electrical Specifications- AC Characteristics and operating Conditions( Synchronous)……………125 Electrical Specifications- Array Characteristics 音垂4音音垂 128 Asynchronous Interface Timing Diagrams………………… ·.··· l29 Synchronous interface Timing diagrams 139 Revision history 音 l61 Rev. i Production -1/19/18 161 Rev. H Production-10/14……,161 Rev.G-7/14 ,16l DF:0900 3415d Micron Technology, Inc reserves the right to change products or specifications without notice. o 2012 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary ccr。n 32Gb, 64G Asynchronous/Synchronous NAND Features Rev.F一4/14∴162 Rev.E-10/13 163 Rev.D-5/13 163 Rev.C-12112∴ 163 Rcv.B-10/12 非·着,垂非·看 163 Rev.A-4/12..…163 DF:0900 3415d Micron Technology, Inc reserves the right to change products or specifications without notice. o 2012 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary ccr。n 32Gb, 64G Asynchronous/Synchronous NAND Features List of tables Table 1: Asynchronous and Synchronous Signal Definitions…,…,…, Table2: Array Addressing for Logical Unit(LUN)…,…,…,…,…,…,…,…,…,…,………,19 Table 3: Asynchronous Interface Mode selection 20 Table 4: Synchronous Interface Mode Selection 30 Table 5: Command set 42 Table 7: Read ID Parameters for Address 20 Table 6: Read id parameters for address ooh 48 48 Table 8 Rcad id paramcters for Address 40h 48 Table 9: ONFI Parameter Page Delinition 51 Table 10: JEDEC Parameter Page Definition 57 Table 11: Feature Address definitions 64 Table 12: Feature Address Olh: Timing Mode 66 Table 13: Feature Addresses 10h and 80h: Programmable Output Drive Strength 67 Table 14: Feature Address 8lh: Programmable r/b# pull-Down Strength Table 15: Feature Address89h: Read Retry…………,…,…,…,…,…,…,…,…,…,… 68 Table 16: Feature Address 90h: Array Operation Mode ..:·....:. 69 Table 17: Status Register Definition∴…………… Table 18: OTP Area details L01 Table 19;: Error Management Details∴……,…,…,…,…,…,…,,,,………,107 Table 20: Shared Pages 108 Table 21: Output Drive Strength Conditions (VccQ=1.7-1.95V) 1l0 Table 22: Output Drive Strength Impedance Values (VccQ=1.7-1.95V Table23: Output Drive Strength Conditions(vccQ=27-36V)…………… IlI Tabe24: Output Drive Strength Impedance values(vcco=27-3.6V)……… Table25:Pull- Up and pull- Down Output Impedance mismatch.…,……,…,,…,……,112 Table 26: Asynchronous Overshoot/Undershoot Parameters..............................113 Table 27: Synchronous Overshoot/Undershoot Parameters Table28: Test Conditions for Input Slew Rate……,…,…,,…,…,…,…,…,…,……,1l4 Table 29: Input Slew Rate(VccQ=1.7-1.95V) 1l4 Table 30: Input Slew Rate (VccQ=2.7-3.6V) 114 Table31: Test Conditions for Output Slew rate∴……… ·非垂 115 Table32: Output Slew rate(Vcco=1.7-1.95V)………115 Table3: Output Slew Rate(VcQ=27-36V)……… l15 Table 34: Power Cycle requirements 116 Table 35: Absolute Maximum Ratings by Device Table 36: Recommended Operating Conditions . .l17 Table37: Valid Blocks per LUN……,……… Table38: Capacitance:132-Bal! BGA Package……,…,…,,,…, 118 Table 39: Capacitance: 48-Pin TSOP Package ....:·····.·····.······:······ Table 40: Test conditions 118 Tablc 41: DC Characteristics and Opcrating Conditions(Asynchronous Intcrfacc) 19 Table 42: DC Characteristics and Operating Conditions(Synchronous Interface)for 3.3VV 着D·垂非D非非非垂 120 Table 43: DC Characteristics and Operating Conditions (Synchronous Interface) for 1.8VVccQ 120 Table 44: DC Characteristics and Operating Conditions(3. 3VV CCQ)… 121 Table46: AC Characteristics: Asynchronous Command, Address,, and data……、∴…………22 Table 45: DC Characteristics and Operating Conditions (1.8VVccQ) l23 Table 47: AC Characteristics: Synchronous Command, Address, and data 125 Table 48: Array Characteristics 着非 ∴128 DF:0900 3415d Micron Technology, Inc reserves the right to change products or specifications without notice. o 2012 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary ccr。n 32Gb, 64G Asynchronous/Synchronous NAND Features List of Figures Figure 1: Part Numbering……………,…,…,,…,…,…,,…,,,,…, Figure2:48- Pin TsoP Type l(Topⅵiew)………,…,…,…,…,…,…,…,…,…,…,…,…,13 Figure 3: 132-Ball BGA(Ball-Down, Top view) 14 Figure4:48- Pin tsop- Type I CPL( Package Code:WP)……… 15 Figure 5: 132-Ball VBGA-12mm x 18mm x lmm (Package Code: J4 Figure6: NAND Flash Die (lun) Functional Block diagram…….….,….,…,…,…,…,,…, Figure 7: Device Organization for Single-Die Package(TSOP, BGA) Figure8: Device Organization for Two- Dic Package(BGA)………,………… 18 Figure9: Array Organiκ ation per Logical Unit(LUN)…….……,…………,……,…,……………………,19 Figure 10: Asynchronous Command Latch Cycle 21 Figure 11: Asynchronous Address Latch Cycle…………………… 22 Figure12: Asynchronous data Input Cycles,…,…,…,…,…,…,…,,…,…,23 Figure 13: Asynchronous Data Output cycles.. 24 Figure I4: Asynchronous Data Output Cycles( DO Mode)…………………… 25 Figure 15:READ/BUSY# Open drain.,…,…,…,…,…,,………,26 Figure16: Fall and rise(Vcco=27-3.6V)…… 27 Figure I7: Fall and rise(VcQ=1.7-1.95V)……………… 27 Figure18: IOL VS Rp(Vc=2.7-3.6V)…………… 非4音 28 Figure 19: IOL VS Rp (VccQ=1.7-1.95V) 28 Figure 20: TC vs ri 29 igure21: Synchronous Bus Idle/ Driving Behavior………………………… 32 Figure 22: Synchronous Command Cycle 33 Figure23: Synchronous Address cycle…… 34 igure24: Synchronous DDR Data Input Cycles…………………………35 Figure25: Synchronous dDr Data Output Cycles.…,…,…,,,, 37 Figure26:R/B# Power- On behavior....,…,…,…,…,………,38 Figure 27: Activating the Synchronous Interface 41 Figure 28: RESET (FFh)Operation 44 Figure29: SYNCHRONOUS RESET(FCh) Operation…,……,…,,…,… 45 Figure 30: RESET LUN (FAh)Operation 46 Figure 31: READ ID (90h)with 00h Address Operation 47 Figure32: READ ID(oh)with20 h Address operation.……,…,…,…,,…,……,47 Figure 33: READ ID(90h)with 40h Address Operation 47 Figure34: READ PARAMETER(ECh) with oc0 h Address Operation for ONFI…………,………………49 Figure 35: READ PARAMETER(ECh)with 40h Address Operation for JEDEC Figure 36: READ UNIQUE ID(EDh)Operation 63 Figure 37: SET FEATURES (EFh)Operation ∴65 Figure38: GET FEATURES(EEh) Operation….………,…,…,…,…,…,…,…,…,…,…,…,…,……,65 Figure39: READ STATUS(70h) Operation…,,…,…,…,…,…,…,,…,…………,72 Figure 40: READ STATUS ENHANCED(78h) Operation .72 Figurc 41: CHANGE READ COLUMN (O5h-EOh)Opcration ·..··:···· Figure42: CHANGE READ COLUMN ENHANCED(06h-EOh) Operation…,…,… 74 Figure 43: CHANGE READ COLUMN ENHANCED (0Oh-05h-EOh)Operation .74 Figure44: CHANGE WRITE COLUMN(85h) Operation………….… ,75 Figure 45: CHANGE ROW ADDRESS(85hOperation 76 Figure 46: READ PAGE (00h-30h)Operation ... 80 Figure 47: READ PAGE CACHE SEQUENTIAL (31h)Operation 81 Figure 48: READ PAGE CACHE RANDOM (0Oh-31h)Operation 83 Figure 49: READ PAGE CACHE LAST (3 Fh)Operation 84 Figure 50: READ PAGE MULTI-PLANE (00h-32h)Operation 86 DF:0900 3415d Micron Technology, Inc reserves the right to change products or specifications without notice. o 2012 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary ccr。n 32Gb, 64G Asynchronous/Synchronous NAND Features Figure5l: Read retry Flow Chart…,…,…,…,,,……,……,,,88 Figure 52: PROGRAM PAGE(80h-10h)Operation 90 Figure 53: PROGRAM PAGE CACHE (80h-15h)Operation(Start) 92 Figure54: PROGRAM PAGE CACHE(8Oh-15h) Operation(End)……… 92 Figurc55: PROGRAM PAGE MULTI- PLANE(80h-llh) Opcration……,…,,, 94 Figure56: ERASE BLOCK(60h-D0h) Operation………,…,…,…,…,…,…,…,…,…,…,……,95 Figure 57: ERASE BLOCK MULTI-PLANE (60h-Dih)Operation...... 96 Figure58: ERASE BLOCK MULTI-PLANE(60h-60h-Doh) Operation…………… 96 Figure 59: COPYBACK READ (00h-35h)Operation 98 Figure 60: COPYBACK READ (00h-35h)with CHANGE READ COLUMN (05h-EOh)Operation .........98 Figure61: COPYBACK PROGRAM(85h-10 h) Operation……… 99 Figure62: COPYBACK PROGRAM(85h-10h) with CHANGE WRITE COLUMn(85h) Operation………,…,9 Figure 63: COPYBACK PROGRAM MULTI-PLANE figure64: PROGRAM OTP PAGE(80h-10h) Operation……………… ∴102 Figurc 65: PROGRAM OTP PAGE (80h-10h) with CHANGE WRITE COLuMn (85h)Opcration .103 Figure 66: PROTECT OTP AREA(80h-10h)Operation ·垂垂非音,垂,音音音垂 103 Figure67: READ OTP PAGE〔00h-30h) Operation………,……,……,…,…,.,……,104 Figure 68: Overshoot Figure69: Undershoot.….,…,….,…,…,…,…,…,…,, Figure70: RESET Operation…… l29 Figure7l: RESET LUN Operation………………129 Figure72: READ STATUS Cycle……,,…,…,…,,…,,… 看·着4·垂 130 Figure 73: READ STATUS ENHANCED Cycle 130 Figure 74: READ PARAMETER PAGE ∴131 Figure75: READ PAGE.,,,,………… 看看着看,垂音D番着·垂 131 Figure76: READ PAGE Operation with CE#“Don' t care”…,,…,…,…,…,,…,……………,132 igure 77: CHANGE READ COLUMN 132 Figure 78: READ PAGE CACHE SEQUENTIAL 133 Figure79: READ PAGE CACHE RANDOM∴………,……,…,…,……,………,…………134 figure80: READ ID Operation∴…………….……….….…… :· 135 Figure8l: PROGRAM PAGE Operation……………135 Figure82: PROGRAM PAGE Operation with Ce#“Don' t care”……,…,…,…,…,… l36 Figure 83: PROGRAM PAGE Operation with CHANGE WRITE COLUMN 136 Figure84: PROGRAM PAGE CACHE………,……………137 Figure85: PROGRAM PAGE CACHE Ending on 15h…… 137 Figure86: COPYBACK… 138 Figure87:上 RASE BLOCK Operation…………………………… l38 Figurc88: SET FEATURES Opcration…… 139 Figure89: READ ID Operation..…,…,…,…,…,…,…,…,…,…,…,140 Figure 90: GET FEATURES Operation 141 Figure9l: RESET(FCh) Operation……………………,…,…,…,…… ..·:········.·,·:·········· 142 Figure92: READ STATUS Cycle…………,…,…,…,…,…,…,…,…,…,…,…,…,…,,…,,…,143 Figure 93: READ STATUS ENHANCED Operation 144 Figure 94: READ PARAMETER PAGE Operation 145 Figure95: READ PAGE Operation…,,…,…,…,…,…,,146 Figure 96: CHANGE READ COLUMN 147 figure97: READ PAGE CACHE SEQUENTIAL(lof2)……… ∴148 Figurc98: READ PAGE CACHE SEQUENTIAL(2of2)…….…,…,…,…,…,…,…,…,…… 149 Figure 99: READ PAGE CACHE RANDOM (1 of2) 音 150 Figure 100: READ PAGE CACHE RANDOM (2 of 2) 150 Figure101: Multi- Plane read page(lof2)…………,…,………… 151 Figure 102: Multi-Plane Read Page(2 of 2) ,152 DF:0900 3415d Micron Technology, Inc reserves the right to change products or specifications without notice. o 2012 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary ccr。n 32Gb, 64G Asynchronous/Synchronous NAND Features Figure103: PROGRAM PAGE Operation(lof2)…… 153 Figure104: PROGRAM PAGE Operation(2of2)…… 153 Figure 105: CHANGE WRITE COLUMN 154 Figure106: Multi- Plane Program Page…………… 155 Figure107: ERASE BLOCK………………,……………… ·.···· 156 Figure 108: COPYBACK(1 of 3) 156 Figure 109: COPYBACK (2 of 3) 157 Figure110: COPYBACK(3of3)………,…,…,…,…,…,…,…,……,………………………157 Figure11l: READ OTP PAGE……,……,…,,… ∴158 Figure 112: PROGRAM OTP PAGE (1 of 2).............................. 159 Figure113: PROGRAM OTP PAGE(2of2)………… 159 igure1l4: PROTECT OTP AREA3……,…,…,…,…,…,,…,…,………160 DF:0900 3415d Micron Technology, Inc reserves the right to change products or specifications without notice. o 2012 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary ccr。n 32Gb, 64Gb Asynchronous/Synchronous NAND Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc (Micron")reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this docu- ment if you obtain the product described herein from any unauthorized distributor or other source not authorized by micron Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi- cally designated by Micron as automotivc-gradc by thcir respective data shccts Distributor and customer/distrib utor shall assume the sole risk and liability for and shall indemnify and hold micron harmless against all claims costs,damages, and expenses and reasonable attorneys'fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use ofnon- automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con ditions of sale between customer/distributor and any customer of distributor /customer (1) state that micron products are not designed or intended for use in automotive applications unless specifically designated by micron as automotive-grade by their respective data sheets and (2)require such customer of distributor/customer to in demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the micron compo- nent could result, directly or indirectly in death, personalinjury, or severe property or environmental damage ("Critical Applications" ). Customer must protect against death, personal injury, and severe property and environ mental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims costs, damages, and expenses and reasonable attorneys fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL- URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMERS SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER S SYSTEM, APPLICATION OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en vironmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges)whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative DF:0900 3415d 10 Micron Technology, Inc reserves the right to change products or specifications without notice. o 2012 Micron Technology, Inc. All rights reserved

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