################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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基于FPGA的FM解调系统.rar
共791个文件
v:78个
txt:67个
coe:44个
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基于xilinx A7系列FPGA实现FM信号调制解调通信系统,包含AD\DA驱动,数字下变频,FM调制解调等模块。源码仅供参考学习使用。
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基于FPGA的FM解调系统.rar (791个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 23KB
elaborate.bat 936B
simulate.bat 862B
compile.bat 830B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
TOP.bit 3.65MB
tb_fir_100k.c 8KB
tb_fir_1M.c 8KB
wave_sin_1024_12bit_signed.coe 6KB
wave_sin_1024_12bit_signed.coe 6KB
wave_sin_1024_12bit_signed.coe 6KB
wave_rec_1024_8bit_signed.coe 6KB
wave_rec_1024_8bit_signed.coe 6KB
wave_rec_1024_8bit_signed.coe 6KB
wave_sin_1024_8bit_signed.coe 5KB
wave_sin_1024_8bit_signed.coe 5KB
wave_sin_1024_8bit_signed.coe 5KB
lpf_1mfs.coe 737B
lpf_1mfs.coe 737B
lpf_1mfs.coe 737B
RCF_Fs5M_Fc20K_1.coe 732B
RCF_Fs5M_Fc20K_1.coe 732B
RCF_Fs5M_Fc20K_1.coe 732B
RCF_Fs5M_Fc20K_1.coe 732B
RCF_Fs5M_Fc20K_1.coe 732B
RCF_Fs5M_Fc20K_1.coe 732B
RCF_Fs5M_Fc20K_1.coe 732B
RCF_Fs5M_Fc20K_1.coe 732B
RCF_Fs5M_Fc20K_1.coe 732B
RCF_Fs5M_Fc20K_1.coe 732B
lpf_Fs100m.coe 616B
lpf_Fs100m.coe 616B
lpf_Fs100m.coe 616B
lpf_Fs5m_150-500k.coe 497B
lpf_Fs5m_150-500k.coe 497B
lpf_Fs5m_150-500k.coe 497B
lpf_Fs5m_150-500k.coe 497B
lpf_Fs5m_150-500k.coe 497B
lpf_Fs5m_150-500k.coe 497B
lpf_Fs5m_150-500k.coe 497B
lpf_Fs5m_150-500k.coe 497B
lpf_Fs5m_150-500k.coe 497B
lpf_Fs5m_150-500k.coe 497B
fir_1M_8M_lpf.coe 454B
fir_1M_8M_lpf.coe 454B
fir_1M_8M_lpf.coe 454B
lpf_Fs50m.coe 402B
lpf_Fs50m.coe 402B
lpf_Fs50m.coe 402B
fir_1M_9M_lpf.coe 376B
fir_1M_9M_lpf.coe 376B
fir_1M_9M_lpf.coe 376B
TOP_routed.dcp 11.46MB
TOP_placed.dcp 9.97MB
TOP_opt.dcp 6.9MB
div_gen_fre.dcp 2.24MB
div_gen_fre.dcp 2.24MB
fir_1M.dcp 1.4MB
fir_1M.dcp 1.4MB
u_ila_0.dcp 1.26MB
u_ila_0.dcp 1.26MB
u_ila_0.dcp 866KB
fir_50m_5M.dcp 795KB
fir_50m_5M.dcp 795KB
fir_100k.dcp 766KB
fir_100k.dcp 766KB
dbg_hub.dcp 347KB
TOP.dcp 172KB
cic_compiler_0.dcp 93KB
cic_compiler_0.dcp 93KB
mult_gen_0.dcp 73KB
mult_gen_0.dcp 73KB
wave_sin.dcp 30KB
wave_sin.dcp 30KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
compile.do 784B
compile.do 776B
compile.do 760B
compile.do 752B
compile.do 719B
compile.do 711B
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- m0_749903572023-07-28这个资源对我启发很大,受益匪浅,学到了很多,谢谢分享~
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