TL/F/5319
MM54HC175/MM74HC175 Quad D-Type Flip-Flop With Clear
January 1988
MM54HC175/MM74HC175
Quad D-Type Flip-Flop With Clear
General Description
This high speed D-TYPE FLIP-FLOP with complementary
outputs utilizes advanced silicon-gate CMOS technology to
achieve the high noise immunity and low power consump-
tion of standard CMOS integrated circuits, along with the
ability to drive 10 LS-TTL loads.
Information at the D inputs of the MM54HC175/
MM74HC175 is transferred to the Q and Q
outputs on the
positive going edge of the clock pulse. Both true and com-
plement outputs from each flip flop are externally available.
All four flip flops are controlled by a common clock and a
common CLEAR. Clearing is accomplished by a negative
pulse at the CLEAR input. All four Q outputs are cleared to a
logical ‘‘0’’ and all four Q
outputs to a logical ‘‘1.’’
The 54HC/74HC logic family is functionally as well as pin-
out compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground.
Features
Y
Typical propagation delay: 15 ns
Y
Wide operating supply voltage range: 2–6V
Y
Low input current: 1 mA maximum
Y
Low quiescent supply current: 80 mA maximum (74HC)
Y
High output drive current: 4 mA minimum (74HC)
Connection Diagram
Dual-In-Line Package
TL/F/5319– 1
Top View
Order Number MM54HC175 or MM74HC175
Truth Table
(Each Flip-Flop)
Inputs Outputs
Clear Clock D Q Q
LXXLH
H
u
HH L
H
u
LL H
HLXQ
0
Q
0
H
e
high level (steady state)
L
e
low level (steady state)
X
e
irrelevant
u
e
transition from low to high level
Q
0
e
the level of Q before the indicated
steady-state input conditions were established
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
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