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高级计算机体系结构10存储器结构(英文).pptx
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高级计算机体系结构10存储器结构(英文).pptx
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Computer Architecture
Super Computing Lab.
本资料来源
Computer Architecture
Super Computing Lab.
Lecture 10:
Memory Hierarchy: Reducing Hit
Time, Main Memory, & Examples
Spring 2010
Super Computing Lab.
Supercomputing Lab.
CA10-L10-3
Review: Reducing Misses
•
3 Cs: Compulsory, Capacity, Conflict Misses
•
Reducing Miss Rate
1. Reduce Misses via Larger Block Size
2. Reduce Misses via Higher Associativity
3. Reducing Misses via Victim Cache
4. Reducing Misses via Pseudo-Associativity
5. Reducing Misses by HW Prefetching Instr, Data
6. Reducing Misses by SW Prefetching Data
7. Reducing Misses by Compiler Optimizations
•
Remember danger of concentrating on just one
parameter when evaluating performance
CPUtime IC CPI
Execution
Memory accesses
Instruction
Miss rate Miss penalty
Clock cycle time
Supercomputing Lab.
CA10-L10-4
Reducing Miss Penalty Summary
•
Five techniques
–
Read priority over write on miss
–
Subblock placement
–
Early Restart and Critical Word First on miss
–
Non-blocking Caches (Hit under Miss, Miss under Miss)
–
Second Level Cache
•
Can be applied recursively to Multilevel Caches
–
Danger is that time to DRAM will grow with multiple levels in
between
–
First attempts at L2 caches can make things worse, since increased
worst case is worse
CPUtime IC CPI
Execution
Memory accesses
Instruction
Miss rate Miss penalty
Clock cycle time
Supercomputing Lab.
CA10-L10-5
Review: Improving Cache
Performance
1. Reduce the miss rate,
2. Reduce the miss penalty, or
3. Reduce the time to hit in the cache
- hit time: read tag + compare
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