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AM335X数据手册(包括AM3358)
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AM335X数据手册(包括AM3358)
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PRODUCTPREVIEW
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717 –OCTOBER 2011
AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs)
Check for Samples: AM3359, AM3358
1 Device Summary
1.1 Features
1234567
– 256KB of L2 Cache with Error Correcting
• Highlights
Code (ECC)
– 500-MHz, 600-MHz, or 720-MHz ARM
®
– 176KB of On-Chip Boot ROM
Cortex™-A8 32-Bit RISC Microprocessor
– 64KB of Dedicated RAM
• NEON™ SIMD Coprocessor
– Emulation/Debug
• 32KB/32KB of L1 Instruction/Data Cache
with Single-Error Detection (parity) • JTAG
• 256KB of L2 Cache with Error Correcting • Embedded Trace Module
Code (ECC)
• Embedded Trace Buffer
– mDDR(LPDDR)/DDR2/DDR3 Support
– Interrupt Controller (up to 128 interrupt
– General-Purpose Memory Support (NAND, requests)
NOR, SRAM, etc.) Supporting Up to 16-bit
• On-Chip Memory (Shared L3 RAM)
ECC
– 64 KB of General-Purpose On-Chip Memory
– SGX530 Graphics Engine
Controller (OCMC) RAM
– Programmable Real-Time Unit Subsystem
– Accessible to all Masters
– Real-Time Clock (RTC)
– Supports Retention for Fast Wake-Up
– Up to Two USB 2.0 High-Speed OTG Ports
• External Memory Interfaces (EMIF)
with Integrated PHY
– mDDR/DDR2/DDR3 Controller:
– 10/100/1000 Ethernet Switch Supporting Up
• mDDR: 200-MHz Clock (400-MHz Data
to Two Ports
Rate)
– Two Controller Area Network Ports (CAN)
• DDR2: 266-MHz Clock (532-MHz Data
– Six UARTs, Two McASPs, Two McSPI, and
Rate)
Two I2C Ports
• DDR3: 303-MHz Clock (606-MHz Data
– 12-Bit Successive Approximation Register
Rate)
(SAR) ADC
• 16-Bit Data Bus
– Up to Three 32-Bit Enhanced Capture
• 1 GB of Total Addressable Space
Modules (eCAP)
• Supports One x16, Two x8, or Four x4
– Up to Three Enhanced High-Resolution PWM
Memory Device Configurations
Modules (eHRPWM)
• Supports Retention for Fast Wake-Up
– Crypto Hardware Accelerators (AES, SHA,
– General-Purpose Memory Controller (GPMC)
PKA, RNG)
• Flexible 8/16-Bit Asynchronous Memory
Interface with Up to seven Chip Selects
• MPU Subsystem
(NAND, NOR, Muxed-NOR, SRAM, etc.)
– 500-MHz, 600-MHz, or 720-MHz ARM
®
• Uses BCH Code to Support 4-Bit, 8-Bit, or
Cortex™-A8 32-Bit RISC Microprocessor
16-Bit ECC
– NEON™ SIMD Coprocessor
• Uses Hamming Code to Support 1-Bit
– 32KB of L1 Instruction Cache with
ECC
Single-Error Detection (parity)
– Error Locator Module (ELM)
– 32KB of L1 Data Cache with Single
• Used in Conjunction with the GPMC to
Error-Detection (parity)
Locate Addresses of Data Errors from
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SmartReflex, DSP/BIOS, XDS are trademarks of Texas Instruments.
3Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.
4ARM is a registered trademark of ARM Ltd or its subsidiaries.
5EtherCAT is a registered trademark of EtherCAT Technology Group.
6POWERVR is a registered trademark of Imagination Technologies Limited.
7All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative or design phase of
Copyright © 2011, Texas Instruments Incorporated
development. Characteristic data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue these products without notice. English Data Sheet: SPRS717
ProdPrev
PRODUCTPREVIEW
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717 –OCTOBER 2011
www.ti.com
Syndrome Polynomials Generated Using LCD Pixel Clock)
a BCH Algorithm
– Power
• Supports 4-Bit, 8-Bit, and 16-Bit per
• Two Non-Switchable Power Domains
512-byte Block Error Location Based on
(Real-Time Clock [RTC], Wake-Up Logic
BCH Algorithms
[WAKE-UP])
• Programmable Real-Time Unit Subsystem
• Three Switchable Power Somains (MPU
(PRUSS)
Subsystem [MPU], SGX530 [GFX],
– Two Programmable Real-Time Units (PRUs) Peripherals and Infrastructure [PER])
• 32-Bit Load/Store RISC Processor • Implements SmartReflex™ Class 2B for
Capable of Running at 200 MHz Core Voltage Scaling Based On Die
Temperature, Process Variation and
• 8 KB Instruction RAM with Single-Error
Performance (Adaptive Voltage Scaling
Detection (parity)
[AVS])
• 8 KB Data RAM with Single-Error
• Dynamic Voltage Frequency Scaling
Detection (parity)
(DVFS)
• Single-Cycle 32-Bit Multiplier with 64-Bit
• Real-Time Clock (RTC)
Accumulator
– Real-Time Date (Day/Month/Year/Day of
• Enhanced GPIO Module Provides
Week) and Time (Hours/Minutes/Seconds)
Shift-In/Out Support and Parallel Latch on
Information
External Signal
– Internal 32.768-kHz Oscillator, RTC Logic
– 12 KB of Shared RAM with Single-Error
and 1.1-V Internal LDO
Detection (parity)
– Independent Power-on-Reset
– Three 120-byte Register Banks Accessible
(RTC_PWRONRSTn) Input
by Each PRU
– Dedicated Input Pin (EXT_WAKEUP) for
– Interrupt Controller Module (INTC) for
External Wake Events
Handling System Input Events
– Programmable Alarm Can be Used to
– Local Interconnect Bus for Connecting
Generate Internal Interrupts to the PRCM (for
Internal and External Masters to the
Wake Up) or Cortex-A8 (for Event
Resources Inside the PRUSS
Notification)
– Peripherals Inside the PRUSS
– Programmable alarm Can be Used with
• One UART Port with Flow Control Pins,
External Output (PMIC_POWER_EN) to
Supports Up to 12 Mbps
Enable the Power Management IC to Restore
• Two MII Ethernet Ports that Support
Non-RTC Power Domains
Industrial Ethernet, such as EtherCAT
®
• Peripherals
• One MDIO Port
– Up to Two USB 2.0 High-Speed OTG Ports
• One Enhanced Capture (eCAP) Module
with Integrated PHY
• Power Reset and Clock Management (PRCM)
– Up to Two Industrial Gigabit Ethernet MACs
Module
(10/100/1000 Mbps)
– Controls the entry and Exit of Stand-By and
• Integrated Switch
Deep-Sleep Modes
• Each MAC Supports MII/RMII/RGMII and
– Responsible for Sleep Sequencing, Power
MDIO Interfaces
Domain Switch-Off Sequencing, Wake-Up
• Ethernet MACs and Switch Can Operate
Sequencing and Power Domain Switch-On
Independent of Other Functions
Sequencing
• IEEE 1588 Precision Time Protocol (PTP)
– Clocks
– Up to Two Controller-Area Network (CAN)
• Integrated 15-35 MHz High-Frequency
Ports
Oscillator Used to Generate a Reference
• Supports CAN Version 2 Parts A and B
Clock for Various System and Peripheral
Clocks – Up to Two Multichannel Audio Serial Ports
(McASP)
• Supports Individual Clock Enable/Disable
Control for Subsystems and Peripherals • Transmit/Receive Clocks Up to 50 MHz
to Facilitate Reduced Power
• Up to Four Serial Data Pins per McASP
Consumption
Port with Independent TX/RX Clocks
• Five ADPLLs to Generate System Clocks
• Supports Time Division Multiplexing
(MPU Subsystem, DDR Interface, USB
(TDM), Inter-IC Sound (I2S), and similar
and Peripherals [MMC/SD, UART, SPI,
Formats
I2C, etc.], L3, L4, Ethernet, GFX [SGX530],
2 Device Summary Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
PRODUCTPREVIEW
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717 –OCTOBER 2011
• Supports Digital Audio Interface anti-Aliasing
Transmission (SPDIF, IEC60958-1, and
• Fully Virtualized Memory Addressing for
AES-3 Formats)
OS Operation in a Unified Memory
• FIFO Buffers for Transmit and Receive Architecture
(256 bytes)
– LCD Controller
– Up to Six UARTs
• Up to 24-Bits Data Output; 8-Bits per
• All UARTs Support IrDA, CIR and RTS, Pixel (RGB)
CTS Flow Control
• Up to WXGA (1366x768) Resolution
• UART1 Supports Full Modem control
• Integrated LCD Interface Display Driver
– Up to Two Master/Slave McSPI serial (LIDD) Controller
Interfaces
• Integrated Raster Controller
• Up to Two Chip Selects
• Integrated DMA Engine to Pull Data from
• Up to 48 MHz the External Frame Buffer without
Burdening the Processor via Interrupts or
– Up to Three MMC/SD/SDIO Ports
a Firmware Timer
• 1-Bit, 4-Bit and 8-Bit MMC/SD/SDIO
• 512-Word Deep Internal FIFO
Modes
• Supported Display Types:
• MMCSD0 has dedicated Power Rail for
1.8-V or 3.3-V Operation – Character Displays - Uses LCD
Interface Display Driver (LIDD)
• Up to 48-MHz Data Transfer Rate
Controller to Program these Displays
• Supports Card Detect and Write Protect
– Passive Matrix LCD Displays - Uses
• Complies with MMC4.3 and SD/SDIO 2.0
LCD Raster Display Controller to
Specifications
Provide Timing and Data for Constant
– Up to Three I2C Master/Slave Interfaces
Graphics Refresh to a Passive Display
• Standard Mode (up to 100 kHz)
– Active Matrix LCD Displays - Uses
• Fast Mode (up to 400 kHz)
External Frame Buffer Space and the
– Up to Four Banks of General-Purpose IO
Internal DMA Engine to Drive
(GPIO)
Streaming Data to the Panel. Maximum
• 32 GPIOs per Bank (Multiplexed with
Resolution is WXGA (1366x768) at
Other Functional Pins)
60-Hz Refresh Rate
• GPIOs Can be Used as Interrupt Inputs
– 12-Bit Successive Approximation Register
(Up to Two Interrupt Inputs per Bank)
(SAR) ADC
– Up to Three External DMA Event Inputs That
• 100K Samples per Second
Can Also be Used as Interrupt Inputs
• Input Can be Selected from any of the
– Seven 32-Bit General-Purpose Timers
Eight Analog Inputs Multiplexed Through
an 8:1 analog Switch
• DMTIMER1 is a 1-ms Timer Used for
Operating System (OS) Ticks
• Can be Configured to Operate as a 4-wire,
5-wire, or 8-wire Resistive Touch Screen
• DMTIMER4 - DMTIMER7 are Pinned Out
Controller (TSC) Interface
– One Watchdog Timer
– Up to Three 32-Bit Enhanced Capture
– SGX530 3D Graphics Engine
Modules (eCAP)
• Tile-Based Architecture Delivering Up to
• Configurable as Three Capture Inputs or
20 MPloy/sec
Three Auxiliary PWM Outputs
• Universal Scalable Shader Engine is a
– Up to Three Enhanced High-Resolution PWM
Multi-Threaded Engine Incorporating
Modules (eHRPWM)
Pixel and Vertex Shader Functionality
• Dedicated 16-Bit Time-Base Counter with
• Advanced Shader Feature Set in Excess
Time and Frequency Controls
of Microsoft VS3.0, PS3.0 and OGL2.0
• Configurable as Six Single-Ended, Six
• Industry Standard API Support of
Dual-Edge Symmetric, or Three
Direct3D Mobile, OGL-ES 1.1 and 2.0,
Dual-Edge Asymmetric Outputs
OpenVG 1.0, and OpenMax
– Up to Three 32-Bit Enhanced Quadrature
• Fine-Grained Task Switching, Load
Pulse Encoder (eQPE) Modules
Balancing and Power Management
• Device Identification
• Advanced Geometry DMA Driven
– Contains Electrical fuse Farm (FuseFarm) of
Operation for Minimum CPU Interaction
Which Some Bits are Factory Programmable
• Programmable High-Quality Image
Copyright © 2011, Texas Instruments Incorporated Device Summary 3
Submit Documentation Feedback
www.ti.com: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
PRODUCTPREVIEW
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717 –OCTOBER 2011
www.ti.com
•
Production ID – Integrates Hardware-Based Mailbox for IPC
and Spinlock for Process Synchronization
• Device Part Number (Unique JTAG ID)
Between the Cortex-A8, PRCM, and Each
• Device Revision (readable by Host ARM)
PRU
• Debug Interface Support
• Mailbox Registers that Generate
– JTAG/cJTAG for ARM (Cortex-A8 and
Interrupts
PRCM), PRU Debug
– Four Initiators (Cortex-A8, PRCM,
– Embedded Trace Module (ETM) and
PRU0, PRU1)
Embedded Trace Buffer (ETB)
• Spinlock has 128 Software-Assigned
– Supports Device Boundary Scan
Lock Registers
– Supports IEEE1500
• Security
• DMA
– Crypto Hardware accelerators (AES, SHA,
– On-Chip Enhanced DMA Controller (EDMA)
PKA, RNG)
has Three Third-Party Transfer Controllers
• Boot Modes
(TPTC) and One Third-Party Channel
– Boot Mode is Selected via Boot
Controller (TPCC), Which Supports Up to 64
Configuration Pins Latched on the Rising
Programmable Logical Channels and Eight
Edge of the PWRONRSTn Reset Input Pin
QDMA Channels. EDMA is Used for:
• Packages:
• Transfers to/from On-Chip Memories
– 298-Pin S-PBGA-N298 package
• Transfers to/from External Storage (EMIF,
(ZCE Suffix), 0.65-mm Ball Pitch
General-Purpose Memory Controller,
– 324-Pin S-PBGA-N324 package
Slave Peripherals)
(ZCZ Suffix), 0.80-mm Ball Pitch
• Inter-Processor Communication (IPC)
1.2 Applications
• Gaming Peripherals
• Home and Industrial Automation
• Consumer Medical Appliances
• Printers
• Smart Toll Systems
• Connected Vending Machines
• Weighing Scales
• Educational Consoles
• Advanced Toys
1.3 Description
The AM335x microprocessors based on the ARM Cortex-A8 are enhanced with image, graphics
processing, peripherals and industrial interface options such as etherCAT and Profibus. The device
supports the following high-level operating systems (OSs), that are available free of charge from TI:
• Linux
®
• Windows
®
CE
• Android™
The AM335x microrocessor contains these subsystems:
• Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor.
• POWERVR
®
SGX Graphics Accelerator subsystem for 3D graphics acceleration to support display and
gaming effects.
• Programmable Real-Time Unit Subsystem (PRUSS) enables the user to create a variety of digital
resources beyond native peripherals of the device. In addition, the PRUSS is separate from the ARM
core. This allows independent operation and clocking to give the device greater flexibility in complex
system solutions.
Note: The subsystem available on this device is the next-generation PRUSS (PRUSSv2).
4 Device Summary Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
PRODUCTPREVIEW
ARM
Cortex-A8
500/600/720 MHz
(A)(B)(C)
32K/32K L1 w/SED
256K L2 w/ECC
176K ROM
64K RAM
Graphics
PowerVR
SGX
3D GFX
Crypto
64K
shared
RAM
24-bit LCD controller (WXGA)
Touch screen controller
Display
PRU subsystem
PRU x2
200 MHz
8K/8K w/SED
12K RAM
w/SED
Peripherals
L3/L4 interconnect
USB 2.0 HS
OTG + PHY x2
CAN x2
(Ver. 2 A and B)
McASP x2
(4 channel)
I C x3
2
SPI x2
UART x6
Serial System Parallel
eDMA
Timers x7
WDT
RTC
eHRPWM x3
eQEP x3
PRCM
eCAP x3
ADC (8 channel)
12-bit SAR
JTAG /
ETM / ETB
Crystal
Oscillator x2
MMC/SD/
SDIO x3
GPIO
EMAC (2-port) 10M/100M/1G
IEEE1588, and switch
(MII, RMII, RGMII)
LPDDR1 / DDR2 / DDR3
(16-bit, 200 / 266 / 303 MHz)
NAND/NOR (16-bit ECC)
Memory interface
A. Nominal voltage condition (1.1 V); available on ZCE and ZCZ packages.
B. Overdrive voltage condition (1.2 V); only available on ZCZ package.
C. Turbo voltage condition (1.26 V); only available on ZCZ package.
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717 –OCTOBER 2011
1.4 Functional Block Diagram
The AM335x microrocessor functional block diagram is shown in Figure 1-1.
Figure 1-1. AM335x Functional Block Diagram
Copyright © 2011, Texas Instruments Incorporated Device Summary 5
Submit Documentation Feedback
www.ti.com: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
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