SH1126驱动芯片规格书资源-CSDN文库

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SH1126

384 X 96 16 Grayscale

Preliminary Dot Matrix OLED/PLED Driver with Controller

1 V1.0

Features

n Support maximum 384 X 96 dot matrix panel with 16

grayscale

n Embedded 384 X 96 X 4bits SRAM

n Operating voltage:

- I/O voltage supply: VDD1 = 1.65V - 3.5V

- Logic voltage supply: VDD2 = 1.65V - 3.5V

VDD1 = VDD2

- DC-DC voltage supply: AVDD = 2.4V - 3.5V

- OLED Operating voltage supply: VPP = 7.0V -14V

n Maximum segment output current: 500mA

n Maximum common sink current: 192mA

n 8-bit 6800-series parallel interface, 8-bit 8080-series

parallel interface, 3 wire/4 wire serial peripheral interface

n 400KHZ fast I

C bus interface

n Programmable frame frequency and multiplexing ratio

n Row re-mapping and column re-mapping (ADC)

n Vertical scrolling

n On-chip oscillator

n Available internal DC-DC converter

n 256-step contrast control on monochrome passive OLED

panel

n Low power consumption

- Sleep mode: < 5mA

n Wide range of operating temperatures: -40 to +85°C

n Available in COG form

General Description

SH1126 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dot-matrix graphic

display system. SH1126 consists of 384 segments, 96 commons with 16 grayscale that can support a maximum display

resolution of 384 X 96. It is designed for Common Cathode type OLED panel.

SH1126 embeds with contrast control, display RAM oscillator and efficient DC-DC converter, which reduces the number of

external components and power consumption. SH1126 is suitable for a wide range of compact portable applications, such as

car audio, and calculator, etc.

SH1126

System Bus Connection Pads

Pad No.

Symbol

I/O

Description

87 CL I/O

This pad is the system clock input. When internal clock is enabled, this pad should be Left open.

The internal clock is output from this pad. When internal oscillator is disabled,

this pad receives display clock signal from external clock source.

73 CLS I

This is the internal clock enable pad.

CLS = “H”: Internal oscillator circuit is enabled.

CLS = “L”: Internal oscillator circuit is disabled (requires external input).

When CLS = “L”, an external clock source must be connected to the CL pad for normal operation.

IM0

IM1

IM2

These are the MPU interface mode select pads.

8080

C 6800 4-wire SPI 3-wire SPI

IM0 0 0 0 0 1

IM1 1 1 0 0 0

IM2 1 0 1 0 0

This pad is the chip select input. When

= “L”, then the chip select becomes active,

and data/command I/O is enabled.

RES

This is a reset signal input pad. When

RES

is set to “L”, the settings are initialized.

The reset operation is performed by the

RES

signal level.

(SA0)

This is the Data/Command control pad that determines whether the data bits are a data or a

command.

A0 = “H”: the inputs at D0 to D7 are treated as display data.

A0 = “L”: the inputs at D0 to D7 are transferred to the command registers.

In I

C interface, this pad serves as SA0 to distinguish the different address of OLED driver.

(

WR/

)

This is a MPU interface input pad.

When connected to an 8080 MPU, this is active LOW. This pad connects to the 8080 MPU

signal. The signals on the data bus are latched at the rising edge of the

signal.

When connected to a 6800 Series MPU: This is the read/write control signal input terminal.

When

WR/

= “H”: Read.

When

WR/

= “L”: Write.

(E)

This is a MPU interface input pad.

When connected to an 8080 series MPU, it is active LOW. This pad is connected to the

signal

of the 8080 series MPU, and the SH1126 data bus is in an output status when this signal is “L”.

When connected to a 6800 series MPU, this is active HIGH. This is used as an enable clock input

of the 6800 series MPU.

92~99

D0 - D7

(SCL)

(SI /SDA)

I/O

This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus.

When the serial interface is selected, then D0 serves as the serial clock input pad (SCL) and

D1serves as the serial data input pad (SI). At this time, D2 to D7 are set to high impedance.

When the I2C interface is selected, then D0 serves as the serial clock input pad (SCL) and D1

serves as the serial data input pad (SDA). At this time, D2 to D7 are set to high impedance.

When the chip select is inactive, D0 to D7 are set to high impedance.

91 FRM O

This pad is No Connection pad. Its signal varies with the frame frequency. Its voltage is equal to

VDD1 when the last common output of every frame is active, and is equal to VSS

during other time.

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