UM11060
LPC540xx User manual
Rev. 1.1 — 4 January 2018 User manual
Document information
Info Content
Keywords LPC540xx, ARM Cortex-M4, 32-bit microcontroller, LCD, Ethernet AVB,
SPIFI, SCT/PWM, USB Host, USB device, CAN FD, I2C, I2S, EMC,
SDRAM controller, DMIC, SDIO interface, SD card interface, LCD
controller, SHA
Abstract LPC540xx User Manual
UM11060 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
User manual Rev. 1.1 — 4 January 2018 2 of 1149
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors
UM11060
LPC540xx User manual
Revision history
Rev Date Description
UM11060 v.1.1 20180104 LPC540xx User manual.
Modifications: • Updated Chapter 10 “LPC540xx I/O pin configuration (IOCON)”.
• Updated Chapter 3 “LPC540xx Boot ROM”.
• Minor changes throughout the document.
UM11060 v.1 20171129 Preliminary version. LPC540xx User manual.
UM11060 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
User manual Rev. 1.1 — 4 January 2018 3 of 1129
1.1 Introduction
The LPC540xx is a family of ARM Cortex-M4 based microcontrollers for embedded
applications featuring a rich peripheral set with very low power consumption and
enhanced debug features.
The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level of support block integration. The
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point processor is integrated into the core.
The LPC540xx family includes 360 KB of on-chip SRAM, a quad SPI Flash Interface
(SPIFI) for expanding program memory, one high-speed and one full-speed USB host and
device controller, Ethernet AVB, LCD controller, Smart Card Interfaces, SD/MMC, CAN
FD, an External Memory Controller (EMC), a DMIC subsystem with PDM microphone
interface and I
2
S, five general-purpose timers, SCTimer/PWM, RTC/alarm timer,
Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), ten flexible serial
communication peripherals (USART, SPI, I
2
S, I
2
C interface), Secure Hash Algorithm
(SHA), 12-bit 5.0 Msamples/sec ADC, and a temperature sensor.
1.2 Features
• ARM Cortex-M4 core (version r0p1):
– ARM Cortex-M4 processor, running at a frequency of up to 180 MHz.
– Floating Point Unit (FPU) and Memory Protection Unit (MPU).
– ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
– Non-maskable Interrupt (NMI) input with a selection of sources.
– Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,
and four watch points. Includes Serial Wire Output and ETM Trace for enhanced
debug capabilities, and a debug timestamp counter.
– System tick timer.
• On-Chip memory:
– Up to 360 KB total SRAM consisting of 160 KB contiguous main SRAM and an
additional 192 KB SRAM on the I&D buses. 8 KB of SRAM bank intended for USB
traffic.
– General-purpose One-Time Programmable (OTP) memory for user application
specific data
• ROM API support:
– In-Application Programming (IAP) and In-System Programming (ISP).
– ROM-based USB drivers (HID, CDC, MSC, and DFU).
UM11060
Chapter 1: LPC540xx Introductory information
Rev. 1.1 — 4 January 2018 User manual
UM11060 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
User manual Rev. 1.1 — 4 January 2018 4 of 1129
NXP Semiconductors
UM11060
Chapter 1: LPC540xx Introductory information
– Supports serial interface booting (UART, I2C, SPI) from an application processor,
automated booting from NOR flash (quad SPIFI, 8/16/32-bit external parallel flash),
and USB booting (full-speed, high-speed).
– Execute in place (XIP) from SPIFI NOR flash (in quad, dual SPIFI mode or
single-bit SPI mode), and parallel NOR flash.
– FRO API for selecting FRO output frequency.
– OTP API for programming OTP memory.
– Random Number Generator (RNG) API.
• Serial interfaces:
– Flexcomm Interface contains up to 11 serial peripherals. Each Flexcomm Interface
(except flexcomm 10, which is dedicated for SPI) can be selected by software to be
a USART, SPI, or I2C interface. Two Flexcomm Interfaces also include an I2S
interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI,
and I2S if supported by that Flexcomm Interface. A variety of clocking options are
available to each Flexcomm Interface and include a shared fractional baud-rate
generator.
– I
2
C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to
1Mbit/s and with multiple address recognition and monitor mode. Two sets of true
I2C pads also support High Speed Mode (3.4 Mbit/s) as a slave.
– Two ISO 7816 Smart Card Interfaces with DMA support.
– USB 2.0 high-speed host/device controller with on-chip high-speed PHY.
– USB 2.0 full-speed host/device controller with on-chip PHY and dedicated DMA
controller supporting crystal-less operation in device mode.
– SPIFI with XIP feature uses up to four data lines to access off-chip SPI/DSPI/QSPI
flash memory at a much higher rate than standard SPI or SSP interfaces.
– Ethernet MAC with MII/RMII interface with Audio Video Bridging (AVB) support and
dedicated DMA controller.
– Two CAN FD modules with dedicated DMA controller.
• Digital peripherals:
– DMA controller with 32 channels and up to 24 programmable triggers, able to
access all memories and DMA-capable peripherals.
– LCD Controller supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistor (TFT) displays. It has a dedicated DMA controller, selectable display
resolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode.
– External Memory Controller (EMC) provides support for asynchronous static
memory devices such as RAM, ROM and flash, in addition to dynamic memories
such as single data rate SDRAM with an SDRAM clock of up to 100 MHz. EMC
bus width (bit) on TFBGA180, TFBGA100, and LQFP100 packages supports up to
8/16 data line wide static memory.
– Secured digital input/output (SD/MMC and SDIO) card interface with DMA support.
UM11060 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
User manual Rev. 1.1 — 4 January 2018 5 of 1129
NXP Semiconductors
UM11060
Chapter 1: LPC540xx Introductory information
– CRC engine block can calculate a CRC on supplied data using one of three
standard polynomials with DMA support.
– Up to 171 General-Purpose Input/Output (GPIO) pins.
– GPIO registers are located on the AHB for fast access. The DMA supports GPIO
ports.
– Up to eight GPIOs can be selected as Pin Interrupts (PINT), triggered by rising,
falling or both input edges.
– Two GPIO Grouped Interrupts (GINT) enable an interrupt based on a logical
(AND/OR) combination of input states.
– CRC engine
• Analog peripherals:
– 12-bit ADC with 12 input channels and with multiple internal and external trigger
inputs and sample rates of up to 5.0 MSamples/sec. The ADC supports two
independent conversion sequences.
– Integrated temperature sensor connected to the ADC.
• DMIC subsystem includes a dual-channel PDM microphone interface with
decimators, filtering, and hardware voice activity detection. The processed output
data can be routed directly to an I
2
S interface if needed.
• Timers
– Five 32-bit general purpose timers/counters. All five timers support up to four
capture inputs and four compare outputs, PWM mode, and external count input.
Specific timer events can be selected to generate DMA requests.
– One SCTimer/PWM with eight input and ten output functions (including capture
and match). Inputs and outputs can be routed to or from external pins and
internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16
match/captures, 16 events, and 16 states.
– 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power
domain. A timer in the RTC can be used for wake-up from all low power modes
including deep power-down, with 1 ms resolution.
– Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at
up to four programmable, fixed rates.
– Windowed Watchdog Timer (WWDT).
– Repetitive Interrupt Timer (RIT) for debug time stamping and for general purpose
use.
• Security features:
– Secure Hash Algorithm (SHA1/SHA2) module supports boot with dedicated DMA
controller.