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### LPC17xx系列微控制器：基于ARM Cortex-M3内核的低功耗高性能解决方案 #### 引言 LPC17xx系列是NXP半导体公司推出的一系列高性能、低功耗微控制器（MCU），该系列MCU基于ARM Cortex-M3内核，提供了丰富的外设接口和功能，如USB、Ethernet、CAN、I2S等，适用于各种嵌入式应用领域。本文将详细介绍LPC17xx系列的关键特性和应用，以及其用户手册中提供的关键信息。 #### 关键特性与功能 LPC17xx系列MCU具有以下关键特性： 1. **ARM Cortex-M3内核**：提供高达120MHz的处理能力，同时保持低功耗特性。 2. **广泛的处理器型号**：包括LPC1769、LPC1768、LPC1767、LPC1766、LPC1765、LPC1764、LPC1759、LPC1758、LPC1756、LPC1754、LPC1752、LPC1751，满足不同性能需求。 3. **高速连接性**：支持USB、Ethernet、CAN，实现高速数据传输和网络通信。 4. **音频支持**：通过I2S接口，可以用于音频输入/输出设备。 5. **灵活的内存管理**：提供多种存储选项，适应不同的存储需求。 6. **高精度定时器和PWM**：适用于精确的时间控制和电机控制应用。 7. **全面的安全特性**：包括加密引擎，为数据安全提供保障。 #### 用户手册概览用户手册UM10360提供了LPC17xx系列的详细信息，包括： 1. **修订历史**：记录了文档的所有更新版本，确保用户了解最新的技术细节。 2. **关键词列表**：列出了所有LPC17xx系列的型号，方便快速定位具体型号的信息。 3. **编辑更新和校对**：确保文档的准确性和专业性，修正可能存在的错误。 4. **新增型号**：例如LPC1758、LPC1767和LPC1768，增加了用户的选择范围。 5. **睡眠模式下的DMA操作**：明确指出在睡眠模式下，DMA操作的限制条件已被移除。 6. **时钟输出功能**：澄清了P1.25端口的功能描述，去除了CLKOUT功能的描述。 7. **Ethernet初始化**：强调外部PHY必须先被初始化，并且接收到PHY时钟信号后，才能进一步初始化Ethernet模块。 8. **UART自动波特率模式**：解释了在自动波特率模式下，UART的分数波特率发生器如何工作。 9. **Motor Control PWM改进**：提供了更准确的RPM计算方法，修正了位置和索引比较寄存器的描述，仅支持“等于”比较。 10. **Flash编程和调试指南**：提供了关于如何有效地编程和调试LPC17xx系列闪存的指导。 #### 结论 LPC17xx系列微控制器以其强大的处理能力和丰富的外设接口，成为低功耗高性能应用的理想选择。用户手册UM10360提供了详尽的技术信息和使用指南，帮助开发人员充分利用LPC17xx系列的优势，实现高效、可靠的嵌入式系统设计。无论是进行高速数据传输、网络通信、音频处理还是精密的电机控制，LPC17xx系列都能提供卓越的性能和灵活性，满足广泛的应用需求。

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UM10360

LPC17xx User manual

Rev. 01 — 10 December 2009 User manual

Document information

Info Content

Keywords LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1759,

LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM Cortex-M3,

32-bit, USB, Ethernet, CAN, I2S, Microcontroller

Abstract LPC17xx user manual

User manual Rev. 01 — 10 December 2009 2 of 835

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors

UM10360

LPC17xx user manual

Revision history

Rev Date Description

1 20091210 LPC17xx user manual revision.

Modifications:

• “Draft” status removed.

• Editorial updates and typographical corrections throughout the user manual.

• LPC1758, LPC1767, and LPC1768 have been added to the keywords list on the front cover,

the ordering information in section Section 1–4

, and the part identification number table in

Section 32–7.11.

• The note about DMA operation in Sleep mode was removed from Section 4–8.1.

• In Table 8–81, the CLKOUT function was removed from the description of P1.25.

• In section the Ethernet chapter, in Section 10–16.1 and Section 10–17.2, it has been noted

that the external PHY must be initialized and PHY clocks received by the Ethernet block prior

to further initialization of the Ethernet block. Also, in Section 10–17.1

, under the heading

"Ownership of descriptors", the sentence about AHB arbitration was removed. A general and

more correct discussion of the subject was added in Section 2–5.

• The UART fractional baud rate generator is disabled in auto baud mode (see

Section 14–14.4.10.1 and Section 15–4.14).

• In section Section 14–4.12 and Section 15–4.16, the description of the value of the DLL

• *** Motor Control PWM ***

• The description of RPM calculation in the QEI chapter (see Section 26–4.3), definitions for the

formula values are added, and the description improved. The description of the position and

index compare registers incorrectly indicated that the less than,equal to, and greater than

compare could be selected. It is changed to only indicate “equal to”.

• A description of Flash signature generation has been added in Section 32–10.

00.07 20090731 Preliminary LPC17xx user manual revision, update to correct errors and improve content.

00.06 20090605 Preliminary LPC17xx user manual revision, first released version.

User manual Rev. 00 — 10 December 2009 4 of 835

NXP Semiconductors

UM10360

Chapter 1: LPC17xx Introductory information

2. Features

Refer to Section 1–4.1 for details of features on specific part numbers.

• ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed

versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory

Protection Unit (MPU) supporting eight regions is included.

• ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

• Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. The combination of an enhanced flash

memory accelerator and location of the flash memory on the CPU local code/data bus

provides high code performance from flash.

• Up to 64 kB on-chip SRAM includes:

– Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance

CPU access.

– Up to two 16 kB SRAM blocks with separate access paths for higher throughput.

These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as

for general purpose instruction and data storage.

• Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer

matrix that can be used with the SSP, I

S, UART, the Analog-to-Digital and

Digital-to-Analog converter peripherals, timer match signals, GPIO, and for

memory-to-memory transfers.

• Multilayer AHB matrix interconnect provides a separate bus for each AHB master.

AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and

the USB interface. This interconnect provides communication with no arbitration

delays unless two masters attempt to access the same slave at the same time.

• Split APB bus allows for higher throughput with fewer stalls between the CPU and

DMA. A single level of write buffering allows the CPU to continue without waiting for

completion of APB writes if the APB was not already busy.

• Serial interfaces:

– Ethernet MAC with RMII interface and dedicated DMA controller.

– USB 2.0 full-speed controller that can be configured for either device, Host, or

OTG operation with an on-chip PHY for device and Host functions and a dedicated

DMA controller.

– Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA

support. One UART has modem control I/O and RS-485/EIA-485 support.

– Two-channel CAN controller.

– Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces

can be used with the GPDMA controller.

– SPI controller with synchronous, serial, full duplex communication and

programmable data length. SPI is included as a legacy peripheral and can be used

instead of SSP0.

– Three enhanced I

C-bus interfaces, one with an open-drain output supporting the

full I

C specification and Fast mode plus with data rates of 1Mbit/s, two with

standard port pins. Enhancements include multiple address recognition and

monitor mode.

User manual Rev. 00 — 10 December 2009 5 of 835

NXP Semiconductors

UM10360

Chapter 1: LPC17xx Introductory information

– I

S (Inter-IC Sound) interface for digital audio input or output, with fractional rate

control. The I

S interface can be used with the GPDMA. The I

S interface supports

3-wire data transmit and receive or 4-wire combined transmit and receive

connections, as well as master clock output.

• Other peripherals:

– 70 (100 pin package) or 52 (80-pin package) General Purpose I/O (GPIO) pins with

configurable pull-up/down resistors, open drain mode, and repeater mode. All

GPIOs are located on an AHB bus for fast access, and support Cortex-M3

bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any

pin of ports 0 and 2 can be used to generate an interrupt.

– 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,

conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can

be used with the GPDMA controller.

– 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA

support.

– Four general purpose timers/counters, with a total of eight capture inputs and ten

compare outputs. Each timer block has an external count input. Specific timer

events can be selected to generate DMA requests.

– One motor control PWM with support for three-phase motor control.

– Quadrature encoder interface that can monitor one external quadrature encoder.

– One standard PWM/timer block with external count input.

– Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a

dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered

backup registers, allowing system status to be stored when the rest of the chip is

powered off. Battery power can be supplied from a standard 3 V Lithium button

cell. The RTC will continue working when the battery voltage drops to as low as

2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.

– Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

– Cortex-M3 system tick timer, including an external clock input option.

– Repetitive interrupt timer provides programmable and repeating timed interrupts.

• Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire

Trace Port options.

• Emulation trace module supports real-time trace.

• Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

• Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C.

• Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0

and PORT2 can be used as edge sensitive interrupt sources.

• Non-maskable Interrupt (NMI) input.

• Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,

CPU clock, or the USB clock.

• The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from

any priority interrupt that can occur while the clocks are stopped in deep sleep,

Power-down, and Deep power-down modes.

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