没有合适的资源?快使用搜索试试~ 我知道了~
ee460m_lab_manual.pdf
需积分: 2 0 下载量 148 浏览量
2020-03-31
23:45:35
上传
评论
收藏 2.28MB PDF 举报
温馨提示
这是美国得克萨斯大学数字设计实验室的verilog入门培训资料,全英文,100多页,内容简单详细、轻松易懂,是不错的新人手册。
资源推荐
资源详情
资源评论
![pdf](https://img-home.csdnimg.cn/images/20210720083512.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![exe](https://img-home.csdnimg.cn/images/20210720083343.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![downloading](https://img-home.csdnimg.cn/images/20210720083646.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![](https://csdnimg.cn/release/download_crawler_static/12289496/bg1.jpg)
The University of Texas at Austin
EE460M Lab Manual
Dept. of Electrical and Computer Eng.
![](https://csdnimg.cn/release/download_crawler_static/12289496/bg2.jpg)
EE 460M Digital Systems Design Using Verilog Lab Manual
Table of Contents
TABLE OF CONTENTS 2
ABOUT THE MANUAL 3
LABS AT A GLANCE 4
LAB POLICIES 5
FREQUENTLY ASKED QUESTIONS 6
LAB ASSIGNMENT #0 16
LAB ASSIGNMENT #1 18
LAB ASSIGNMENT #2 22
LAB ASSIGNMENT #3 27
LAB ASSIGNMENT #4 4
LAB ASSIGNMENT #5 4
LAB ASSIGNMENT #6 13
LAB ASSIGNMENT #7 18
LAB ASSIGNMENT #8A 2
LAB ASSIGNMENT #8B 22
LAB ASSIGNMENT #9 25
LAB ASSIGNMENT #10 28
APPENDIX 31
LAB ASSIGNMENT – ARM PROCESSOR 32
![](https://csdnimg.cn/release/download_crawler_static/12289496/bg3.jpg)
EE 460M Digital Systems Design Using Verilog Lab Manual
About the manual
This document was created by consolidation of the various lab documents being used for EE460M
(Digital Design using Verilog). It is intended to serve as a lab manual for students enrolled in EE460M
at the University of Texas at Austin.
The creation process started towards the end of Spring 2011 and was accomplished by Aman Arora
(TA, EE460M) under the guidance of Prof. Lizy John. In its present form, this document includes
several changes (additions, deletions and modifications) incorporated over three semesters – Spring
2011, Fall 2011,Spring 2012. During the Spring/Fall 2013 semesters, all the labs were translated from
VHDL to Verilog by Daniel Arulraj.
Several important modifications include:
1. Re-organization of Lab#1 and Lab#2 to remove several unimportant and quaint problems
2. Consolidation of tutorials which were spread over Lab#1 and Lab#2 into Lab#0
3. Addition of Lab#6B, which caters to design for test (DFT) concepts
4. Changes in values/design parameters in various labs
5. Re-organization of Lab#5 into three parts
6. Adding the ARM processor lab and the bowling score keeper lab in the appendix
7. Addition of several important details to improve clarity
a. Mostly answers to students doubts
b. Several diagrams
c. Additional explanations
8. Convert the lab manual to Verilog
9. Added Lab#8,9,10
This document is currently maintained by Daniel Arulraj. He can be contacted through email at
daniel.arulraj@utexas.edu. Please write to him in case of any questions or concerns or suggestions.
Important: Do not print this entire document. This document will be updated during the semester.
![](https://csdnimg.cn/release/download_crawler_static/12289496/bg4.jpg)
EE 460M Digital Systems Design Using Verilog Lab Manual
Labs at a glance
S.No.
Brief Description
Objective
Duration
Points
Possible
0
Tutorials – ModelSim and
Xilinx ISE and Nexys2
Board
Introduction to digital design
using FPGAs. Introduction to
simulation and synthesis.
1 week
50
1
Subtractor and ALU
Simple combinational circuit
design
1 week
100
(40+40+20)
2
Excess-3 code converter
and BCD counter
Simple sequential circuit design
1 week
100
(40+30+30)
3
Package sorter and
Traffic Light Controller
More digital design. Introduction
to testbenches.
1.5 weeks
120
(20+50+50)
4
Parking Meter
Advanced digital design.
Interfacing with 7-segment
display and push buttons.
2 weeks
150
5
A basic SNAKE game
Interfacing with PS/2 Keyboard
and VGA display
2 weeks
180
(50+50+80)
6
Stack Calculator
Using Block RAMs on FPGAs
1 week
100
7
MIPS Processor
Basic microprocessor design
2 weeks
150
8
Memory BIST
Understanding JTAG and BIST
1 week
100
9-OPT
Bowling Score Keeper
State machines, logic design
2 weeks
HW (6%)
10-OPT
Floating Point Unit
Arithmetic Units, logic design
1.5 weeks
HW (4%)
Important: Please check the schedule sheet on Canvas for the lab due dates
The OPTIONAL labs (9 and 10) are an alternate for paper and pencil homeworks.
![](https://csdnimg.cn/release/download_crawler_static/12289496/bg5.jpg)
EE 460M Digital Systems Design Using Verilog Lab Manual
Lab Policies
1. You will (have access to and) work in the lab in ENS 302. This is also where TA office hours will be held.
2. This document, available on Canvas, will serve as the lab manual for the entire semester. The document
contains all the lab information you need to do the labs (except for few codes in labs 6 and 7). You can
work on your own pace throughout the semester, but you have to follow the due dates for submission
(listed in the schedule document) and the check out procedures.
3. All communication will be done through Canvas. So, please keep checking Canvas for notifications and
updates. Important information will also be emailed.
4. 15-minute lab discussion sessions will be held at appropriate dates (listed in the schedule document)
before the lecture. These will be conducted by the TAs. It is advisable to read about that lab from the lab
manual before coming to the class, so that you are better prepared to ask questions and resolve doubts.
5. Labs 0, 1 and 2 are to be done individually. Labs 3 through 7 can be done in groups of two. Also, working in
groups does not mean that you work on separate parts of the lab. Both the group members are supposed
to know and answer questions about all parts of the lab. You can switch partners whenever you want.
6. Grading will occur in two parts: submission and demo (checkout).
7. For submission, upload all relevant files (specified with each lab under the ‘Submission Details’ section) via
Canvas. One of the members from each group should log into Canvas and go to “Assignment” section and
then upload all the necessary files under the appropriate link.
8. Lab due dates (submission dates) are specified in the course schedule document on Canvas.
9. After you submit your files, you have to demonstrate your designs to one of the TA’s in the ENS 302 lab.
Once the lab is submitted, DO NOT make changes! You must demo with the code you submitted. In the
event you decide to change the code for the demo, the day of the demo will be considered the turn-in
date, and the appropriate late penalty will be applied.
10. A checkout sign-up sheet is available on Canvas. After every lab due date, the TAs will email the class to
sign-up for a checkout slot. Put your name in that sign-up sheet and reserve a time-slot for your check out.
Please reach the lab at least 5 minutes before your slot. In case of group labs (lab 3 and above), only one
member of the group should submit the files but both members of a group must checkout together. So,
the entries in the checkout slot registration sheet should contain two names.
11. In case you miss your check out slot, you can check out for that lab during office hours anytime before the
next lab’s due date. In other words, the TA’s will not entertain requests for checking out labs older than
the previous lab.
12. The possible points for each lab are mentioned in the ‘Labs at a glance’ section of this manual. Late
submissions (not late checkouts) will lead to penalty according to the following rules:
a. One day late submission – less 10% of your normal score
b. Two day late submission – less 20% of your normal score
c. Three day late submission – less 30% of your normal score
Submissions late by more than 3 days will not be accepted and you will be marked zero (unless you have
taken permission from the professor).
13. Sundays are not counted for late submissions. So, if a lab is due on Saturday and you submit it on Monday,
it will be considered 1-day late submission.
剩余105页未读,继续阅读
资源评论
![avatar-default](https://csdnimg.cn/release/downloadcmsfe/public/img/lazyLogo2.1882d7f4.png)
![avatar](https://profile-avatar.csdnimg.cn/1a059df2ab374e769e8a4f71623a9b66_qq_24916381.jpg!1)
JAD7998
- 粉丝: 58
- 资源: 30
上传资源 快速赚钱
我的内容管理 展开
我的资源 快来上传第一个资源
我的收益
登录查看自己的收益我的积分 登录查看自己的积分
我的C币 登录后查看C币余额
我的收藏
我的下载
下载帮助
![voice](https://csdnimg.cn/release/downloadcmsfe/public/img/voice.245cc511.png)
![center-task](https://csdnimg.cn/release/downloadcmsfe/public/img/center-task.c2eda91a.png)
最新资源
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
![feedback](https://img-home.csdnimg.cn/images/20220527035711.png)
![feedback](https://img-home.csdnimg.cn/images/20220527035711.png)
![feedback-tip](https://img-home.csdnimg.cn/images/20220527035111.png)
安全验证
文档复制为VIP权益,开通VIP直接复制
![dialog-icon](https://csdnimg.cn/release/downloadcmsfe/public/img/green-success.6a4acb44.png)