基于FPGA设计的秒表源码+全部资料齐全_fpga秒表设计资源-CSDN文库

共354个文件

xml：187个

v：30个

pb：18个

版权申诉

FPGA

课程设计

160 浏览量 2024-05-13 19:38:05 上传评论收藏 1.28MB ZIP 举报

资源推荐

资源详情

资源评论

收起资源包目录

基于FPGA设计的秒表源码+全部资料齐全（354个子文件）

__synthesis_is_complete__ 0B

elaborate.bat 901B

compile.bat 824B

simulate.bat 783B

runme.bat 229B

VGA_Top.bit 2.09MB

xsim_1.c 5KB

xsim.dbg 8KB

VGA_Top_routed.dcp 357KB

VGA_Top_placed.dcp 316KB

VGA_Top_opt.dcp 222KB

VGA_Top.dcp 104KB

xsimk.exe 87KB

usage_statistics_webtalk.html 34KB

usage_statistics_ext_xsim.html 3KB

.xsim_webtallk.info 64B

xsimSettings.ini 1KB

xsim.ini 40B

webtalk.jou 741B

webtalk_6524.backup.jou 740B

vivado.jou 635B

vivado.jou 629B

ISEWrap.js 7KB

rundef.js 1KB

runme.log 32KB

runme.log 23KB

webtalk.log 810B

webtalk_6524.backup.log 809B

elaborate.log 546B

xsimkernel.log 314B

simulate.log 50B

xvlog.log 0B

compile.log 0B

xsimcrash.log 0B

W.lpr 343B

README.md 183B

xsim.mem 4KB

xsim_0.win64.obj 31KB

xsim_1.win64.obj 3KB

vivado.pb 59KB

route_design.pb 11KB

place_design.pb 11KB

opt_design.pb 8KB

write_bitstream.pb 3KB

init_design.pb 2KB

xelab.pb 942B

VGA_Top_power_summary_routed.pb 722B

VGA_Top_utilization_placed.pb 276B

VGA_Top_utilization_synth.pb 276B

vivado.pb 149B

VGA_Top_methodology_drc_routed.pb 53B

VGA_Top_timing_summary_routed.pb 52B

VGA_Top_route_status.pb 44B

VGA_Top_drc_opted.pb 37B

VGA_Top_drc_routed.pb 37B

VGA_Top_bus_skew_routed.pb 30B

xvlog.pb 16B

Top_vlog.prj 371B

xsim.reloc 2KB

xsim.rlx 802B

xil_defaultlib.rlx 596B

VGA_Top_io_placed.rpt 72KB

VGA_Top_methodology_drc_routed.rpt 33KB

VGA_Top_clock_utilization_routed.rpt 17KB

VGA_Top_utilization_placed.rpt 9KB

VGA_Top_power_routed.rpt 8KB

VGA_Top_timing_summary_routed.rpt 8KB

VGA_Top_utilization_synth.rpt 7KB

VGA_Top_control_sets_placed.rpt 6KB

VGA_Top_drc_routed.rpt 2KB

VGA_Top_drc_opted.rpt 2KB

VGA_Top_bus_skew_routed.rpt 871B

VGA_Top_route_status.rpt 588B

VGA_Top_power_routed.rpx 177KB

VGA_Top_methodology_drc_routed.rpx 53KB

VGA_Top_timing_summary_routed.rpx 33KB

VGA_Top_drc_routed.rpx 2KB

VGA_Top_drc_opted.rpx 2KB

VGA_Top_bus_skew_routed.rpx 1KB

.route_design.begin.rst 181B

.opt_design.begin.rst 181B

.write_bitstream.begin.rst 181B

.place_design.begin.rst 181B

.init_design.begin.rst 181B

.vivado.begin.rst 179B

.vivado.end.rst 0B

.init_design.end.rst 0B

.Vivado_Implementation.queue.rst 0B

.write_bitstream.end.rst 0B

.route_design.end.rst 0B

.opt_design.end.rst 0B

.place_design.end.rst 0B

.vivado.end.rst 0B

.Vivado_Synthesis.queue.rst 0B

xsim.rtti 190B

@top.sdb 8KB

共 354 条

REM REM Vivado(TM) REM htr.txt: a Vivado-generated description of how-to-repeat the REM the basic steps of a run. Note that runme.bat/sh needs REM to be invoked for Vivado to track run status. REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. REM vivado -log VGA_Top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source VGA_Top.tcl -notrace

评论收藏

内容反馈

版权申诉