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Title

Size Document Number Rev

Date: Sheet

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Homa

-1

BLOCK DIAGRAM

157Thursday, April 03, 2008

970

Title

Size Document Number Rev

Date: Sheet

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Homa

-1

BLOCK DIAGRAM

157Thursday, April 03, 2008

970

Title

Size Document Number Rev

Date: Sheet

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Homa

-1

BLOCK DIAGRAM

157Thursday, April 03, 2008

970

Mobile CPU

Cantiga

HOST BUS 667/800/1066MHz@1.05V

DDR2

667/800 MHz

DDR2

667/800MHz

ICH9M

X4 DMI

400MHz

C-Link0

ODD SATA

HDD SATA

SATA

Mini USB

Blue Tooth

Finger

Printer

Camera

USB

4 Port

USB

PCMCIA

SLOT

KBC

WPC775

Winbond

INT.

Touch

Pad

Winbond

W25X80

BIOS

Launch

Buttom

DEBUG

CONN.

LPC

LPC BUS

a/b/g/n

Mini Card

PCIex1

Kedron

BCM5764M

LAN

Giga LAN

TXFM RJ45

New card

PWR SW

TPS2231

a/b/g/n

Mini Card

Kedron

C Link1

MS/MS Pro/xD

/MMC/SD

5 in 1

VGA Borad

CRT

LCD

HDMI

CLK GEN.

ICS 9LPRS365

EMC2102

RealTek

ALC268

Line In

MIC In

MDC Card

AZALIA

MODEM

Line Out

(No-SPDIF)

RJ11

Port Replicator

AGTL+ CPU I/F

DDR Memory I/F

INTEGRATED GRAHPICS

LVDS, CRT I/F

6 PCIe ports

PCI/PCI BRIDGE

ACPI 2.0

4 SATA

12 USB 2.0/1.1 ports

PCIex16

667/800 MHz

Cardbus

OZ711MZ

PCI

ETHERNET (10/100/1000MbE)

High Definition Audio

LPC I/F

Serial Peripheral I/F

Matrix Storage Technology(DO)

Active Managemnet Technology(DO)

Penryn

4, 5

6,7,8,9,10,11

12,13

20,21,22,23

33 33

35 35

42 42

Homa (TM15") Block Diagram

USBX4

Project code: 91.4Z401.001

PCB P/N : 48.4Z401.011

REVISION : 07245-1

TOP

VCC

GND

BOTTOM

PCB STACKUP

DCBATOUT

SYSTEM DC/DC

5V_S5

INPUTS

SYSTEM DC/DC

TPS51125

5V_S5(7A)

OUTPUTS

TPS51100

DDR_VREF_S3

(1.5A)

3D3V_S5(7A)

1D8V_S3(16A)

DCBATOUT

1D05V_S0(16A)

INPUTS OUTPUTS

TPS51124

DDR_VREF_S3_1

G9131

3D3V_S0 2D5V_S0

(300mA)

APL5912

1D8V_S3 1D5V_S0

(2.5A)

VCC_CORE_S0

0~1.3V

38A

OUTPUTS

CPU DC/DC

INPUTS

DCBATOUT

CHARGER

OUTPUTSINPUTS

CHG_PWR

DCBATOUT

UP+5V

5V 100mA

18V 6.0A

BQ24750

ISL6266A

HP OUT

LINE IN

MIC IN

CRT

DVI

RJ45

VCC_CORE_S0

0~1.3V

5.5A

OUTPUTS

GFX DC/DC

INPUTS

DCBATOUT

ISL6263

G1454

OP AMP

INT.SPKR

G1412

OP AMP

4 4

3 3

2 2

1 1

Title

Size Document Number Rev

Date: Sheet

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Homa

-1

Reference

257Thursday, April 03, 2008

970

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Homa

-1

Reference

257Thursday, April 03, 2008

970

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Homa

-1

Reference

257Thursday, April 03, 2008

970

1 = TLS cipher suite with

confidentiality (default)

0 = Transport Layer Security (TLS) cipher

suite with no confidentiality

Cantiga chipset and ICH9M I/O controller

Hub strapping configuration

page 218

Intel Management

engine Crypto strap

CFG6

Reserved, Rising Edge

of PWROK.

This signal has a weak internal pull-down.

This signal should not be pulled high.

GPIO49

SPI_MOSI

GPIO33/

HDA_DOCK

_EN#

SATALED#

SPKR

TP3

CFG9

(Default)

CFG16

0 = LFP Disabled (Default)

Local Flat Panel

(LFP) Present

CFG19

CFG20

SDVO_CTRLDATA

1 = Dynamic ODT Enabled

0 = Dynamic ODT Disabled

1= LFP Card Present; PCIE disabled

L_DDC_DATA

FSB Dynamic ODT

DMI Lane Reversal

NOTE:

PCIE config2 bit2,

Rising Edge of PWROK.

GNT2#/

GPIO53

Sets bit0 of RPC.PC(Config Registers:Offset 224h)

Top-Block

Swap Override.

Rising Edge of PWROK.

GNT0#:

SPI_CS1#/

GPIO58

0 = Reverse Lanes,15->0,14->1 ect..

Boot BIOS Destination

Selection 0:1.

Rising Edge of PWROK.

Tying this strap low configures DMI for ESI-

compatible operation. This signal has a weak

internal pull up. ESI compatible mode is for

server platforms only.This signal should not

be pulled low for desttop and mobile.

HDA_SDOUT

HDA_SYNC

GNT3#/

GPIO55

Signal

Sampled low:Top-Block Swap mode(inverts A16 for

all cycles targeting FWH BIOS space).

Note: Software will not be able to clear the

Top-Swap bit until the system is rebooted

without GNT3# being pulled down.

This signal has a weak internal pull-up.

XOR Chain Entrance/

PCIE Port Config 1bit1,

Rising Edge of PWROK

1= Normal operation(Default):Lane

Numbered in order

Allows entrance to XOR Chain testing when TP3

pulled low.When TP3 not pulled low at rising edge

of PWROK,sets bit1 of RPC.PC(Config Registers:

offset 224h). This signal has weak internal pull-down

PCIE config 1 bit 0,

Rising Edge of PWROK.

GPIO20

Usage/When Sampled

ESI Strap (Server Only)

Rising Edge of PWROK

Comment

0 = Only Digital Display Port

or PCIE is operational (Default)

1 =Digital display Port and PCIe are

operting simulataneously via the PEG port

0 =No SDVO Card Present (Default)

1 = SDVO Card Present

page 31

DMI Termination Voltage,

Rising Edge of PWROK.

The signal is required to be low for desktop

applications and required to be high for

mobile applications.

Signal has weak internal pull-up. Sets bit 27

of MPC.LR(Device 28:Function 0:Offset D8)

CFG[2:0]

CFG[4:3]

CFG8

CFG[15:14]

CFG[18:17]

CFG5

Pin Name

011 = FSB667

FSB Frequency

Select

0 = DMI x2

others = Reserved

Reserved

(Default)

1 = DMI x4

Strap Description

DMI x2 Select

iTPM Host

Interface

Configuration

Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)

This signal has a weak internal pull-down.

GNT1#/

GPIO51

Integrated TPM Enable,

Rising Edge of CLPWROK

Sample low: the Integrated TPM will be disabled.

Sample high: the MCH TPM enable strap is sampled

low and the TPM Disable bit is clear, the

Integrated TPM will be enable.

Flash Descriptor

Security Override Strap

Rising Edge of PWROK

PCI Express Lane

Reversal. Rising Edge

of PWROK.

No Reboot.

Rising Edge of PWROK.

XOR Chain Entrance.

Rising Edge of PWROK.

This signal should not be pull low unless using

XOR Chain testing. It has a weak internal pull up.

If sampled high, the system is strapped to the

"No Reboot" mode(ICH9 will disable the TCO Timer

system reboot feature). The status is readable

via the NO REBOOT bit.

ICH9M Functional Strap Definitions

Controllable via Boot BIOS Destination bit

(Config Registers:Offset 3410h:bit 11:10).

GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

page 92

PCI Routing

Sampled low:the Flash Descriptor Security will be

overridden. If high,the security measures will be

in effect.This should only be enabled in manufacturing

environments using an external pull-up resister.

SDVO Present

Montevina Platform Design guide 22339 0.5

LAN BCM5764MKMLG

USB Table

0 0AD25RTS5158

INT REQ

G:CARDBUS

GNTIDSEL

LANE2

LANE1

MiniCard WLAN

PCIE Routing

010 = FSB800

000 = FSB1066

LANE3 MiniCard Roboson

ICH9 EDS 642879 Rev.1.5

ICH9M

BATTERY

KBC

Thermal

MXM

SMBC_G792

BAT_SCL

SMB_CLK

NEW Card

SMBC_ICH

CK505

DDR

CFG7

SMBus

ICH9 EDS 642879 Rev.1.5 page 97

ICH9M Integrated Pull-up

and Pull-down Resistors

SIGNAL Resistor Type/Value

HDA_BIT_CLK

HDA_RST#

HDA_SDIN[3:0]

HDA_SDOUT

HDA_SYNC

GNT[3:0]#/GPIO[55,53,51]

GPIO[20]

LAD[3:0]#/FHW[3:0]#

LDRQ[0]

PME#

PWRBTN#

SATALED#

LAN_RXD[2:0]

LDRQ[1]/GPIO23

TP[3]

SPKR

GLAN_DOCK#

SPI_CS1#/GPIO58/CLGPIO6

USB[11:0][P,N]

CL_RST0#

SPI_MOSI

SPI_MISO

TACH_[3:0]

PULL-DOWN 20K

PULL-DOWN 15K

The pull-up or pull-down active when configured for native

GLAN_DOCK# functionality and determined by LAN controller

PULL-UP 20K

PULL-UP 15K

PULL-UP 20K

PULL-DOWN 20K

GPIO[49]

HDA_DOCK_EN#/GPIO33

CL_DATA[1:0]

CL_CLK[1:0]

DPRSLPVR/GPIO16

ENERGY_DETECT

PULL-DOWN 20K

PULL-UP 20K

PULL-UP 10K

PULL-UP 20K

0= The iTPM Host Interface is enabled(Note2)

1=The iTPM Host Interface is disalbed(default)

PCIE Graphics Lane

CFG10 PCIE Loopback enable

0 = Enable (Note 3)

1= Disabled (default)

1 = Reverse Lanes

DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)

DMI x2 mode[MCH -> ICH]:(3->0,2->1)

0 = Normal operation(Default):

Lane Numbered in Order

Digital Display Port

(SDVO/DP/iHDMI)

Concurrent with PCIe

1. All strap signals are sampled with respect to the leading edge of

the (G)MCH Power OK (PWROK) signal.

2. iTPM can be disabled by a 'Soft-Strap' option in the

Flash-decriptor section of the Firmware. This 'Soft-Strap' is

activated only after enabling iTPM via CFG6.

Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

LANE4 NewCard

USB4

USB2

USB1

USB3

Pair

MINIC1

USB

Device

MINIC2

9 NEW1

Bluetooth

DOCK USB

WEBCAM

LAN MiniCard

WLAN

MiniCard

Roboson

CFG12 ALLZ

0 = ALLZ mode enabled (Note 3)

1 = Disabled (default)

CFG13 XOR

0 = XOR mode enabled (Note 3)

1 = Disabled (default)

3. Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.

4 4

3 3

2 2

1 1

3D3V_CLKGEN_S0

3D3V_48MPWR_S0 3D3V_CLKPLL_S0

DREFCLK_1

DREFCLK#_1

DREFSSCLK#_1

DREFSSCLK_1

PCLKCLK1

PCLKCLK2

PCLKCLK3

PCLKCLK4

PCLKCLK5

CPU_SEL2_R

CLK48

GEN_XTAL_OUT_R

GEN_XTAL_IN

3D3V_CLKPLL_S0

3D3V_48MPWR_S0

3D3V_CLKGEN_S0

GEN_XTAL_OUT

CLK48_ICH

PCLK_KBC

PCLK_PCM

PCLK_ICH

PCLK_FWH

CLK_ICH14

DREFSSCLK#

DREFCLK

DREFCLK#

DREFSSCLK

PCLKCLK2

PCLKCLK4

PCLKCLK5

PCLKCLK4

PCLKCLK3

PCLKCLK0

CR#_H

CR#_G

PCLKCLK0

PCLKCLK1

CR#_G

CR#_H

CPU_SEL2_R

3D3V_S0

1D05V_S0

3D3V_S0

DREFCLK 7

DREFCLK# 7

DREFSSCLK# 7

DREFSSCLK 7

CLK_PCIE_SATA 21

CLK_PCIE_SATA# 21

CLK_PCIE_NEW 36

CLK_PCIE_NEW# 36

CLK_MCH_BCLK 6

CLK_MCH_BCLK# 6

CLK_CPU_BCLK 4

CLK_CPU_BCLK# 4

SMBD_ICH12,13,24

SMBC_ICH12,13,24

PM_STPCPU#22

PM_STPPCI#22

CLK_PWRGD22

CLK_ICH1422

CPU_SEL14,7

CLK48_ICH22

CPU_SEL04,7

PCLK_O232

PCLK_PCM31

PCLK_ICH22

PCLK_KBC42

PCLK_FWH43

CLK_PCIE_MINI2 38

CLK_PCIE_MINI2# 38

CLK_MCH_3GPLL 7

CLK_MCH_3GPLL# 7

CLK_PCIE_PEG 35

CLK_PCIE_PEG# 35

CLK_PCIE_LAN# 33

CLK_PCIE_LAN 33

CLK_PCIE_ICH 22

CLK_PCIE_ICH# 22

CLK_PCIE_MINI1 38

CLK_PCIE_MINI1# 38

CLK_MCH_OE#7

SATACLKREQ#22

MXM_CLKREQ#35

LAN_CLKREQ#33

CPU_SEL24,7

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Clock Generator

357Thursday, April 03, 2008

Homa

-1

970

Title

Size Document Number Rev

Date: Sheet

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Clock Generator

357Thursday, April 03, 2008

Homa

-1

970

Title

Size Document Number Rev

Date: Sheet

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Clock Generator

357Thursday, April 03, 2008

Homa

-1

970

PIN NAME DESCRIPTION

Byte 5, bit 7

0 = PCI0 enabled (default)

1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair

Byte 5, bit 6

0 = CR#_A controls SRC0 pair (default),

1= CR#_A controls SRC2 pair

Byte 5, bit 5

0 = PCI1 enabled (default)

1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair

Byte 5, bit 4

0 = CR#_B controls SRC1 pair (default)

1= CR#_B controls SRC4 pair

PCI1/CR#_B

0 = Overclocking of CPU and SRC Allowed

1 = Overclocking of CPU and SRC NOT allowed

PCI2/TME

0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96#

1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0#

PCI4/27M_SEL

ICS9LPRS365YGLFT setting table

0 =SRC8/SRC8#

1 = ITP/ITP#

PCI_F5/ITP_EN

PCI3

PCI0/CR#_A

PIN NAME DESCRIPTION

Byte 5, bit 3

0 = SRC3 enabled (default)

1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair

Byte 5, bit 2

0 = CR#_C controls SRC0 pair (default),

1= CR#_C controls SRC2 pair

Byte 5, bit 1

0 = SRC3 enabled (default)

1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair

Byte 5, bit 0

0 = CR#_D controls SRC1 pair (default)

1= CR#_D controls SRC4 pair

SRCC3/CR#_D

SRCC11/CR#_G

SRCT11/CR#_H

SRCT3/CR#_C

Byte 6, bit 7

0 = SRC7# enabled (default)

1= CR#_F controls SRC6

Byte 6, bit 6

0 = SRC7 enabled (default)

1= CR#_F controls SRC8

Byte 6, bit 4

0 = SRC11 enabled (default)

1= CR#_H controls SRC10

Byte 6, bit 5

0 = SRC11# enabled (default)

1= CR#_G controls SRC9

SRCC7/CR#_E

SRCT7/CR#_F

SEL1

FSB

SEL0

FSA

133M

100M

166M

800M

667M

200M

CPU

SEL2

FSC

FSB

1067M266M

00 0

533M

CL=20pF±0.2pF

EMI capacitor

-1

EC58

Do Not Stuff

EC58

Do Not Stuff

C248

SCD1U16V2ZY-2GP

C248

SCD1U16V2ZY-2GP

RN41

SRN0J-6-GP

UMA

RN41

SRN0J-6-GP

UMA

C242

SCD1U16V2ZY-2GP

C242

SCD1U16V2ZY-2GP

1 2

R204

Do Not Stuff

R204

Do Not Stuff

1 2

R220

Do Not Stuff

R220

Do Not Stuff

C214

SC4D7U10V5ZY-3GP

C214

SC4D7U10V5ZY-3GP

C252

SCD1U16V2ZY-2GP

C252

SCD1U16V2ZY-2GP

1 2

EC71

Do Not Stuff

EC71

Do Not Stuff

C239

SCD1U16V2ZY-2GP

C239

SCD1U16V2ZY-2GP

X-14D31818M-44GP

1ST = 82.30005.891

82.30005.951

X-14D31818M-44GP

1ST = 82.30005.891

82.30005.951

1 2

EC59

Do Not Stuff

EC59

Do Not Stuff

C235

SCD1U16V2ZY-2GP

C235

SCD1U16V2ZY-2GP

R208 Do Not Stuff

1 2

R658

Do Not Stuff

DIS_GM

R658

Do Not Stuff

DIS_GM

C251

SCD1U16V2ZY-2GP

C251

SCD1U16V2ZY-2GP

1 2

EC69

Do Not Stuff

EC69

Do Not Stuff

1 2

R242

Do Not Stuff

R242

Do Not Stuff

1 2

C244

SC27P50V2JN-2-GP

C244

SC27P50V2JN-2-GP

1 2

R659

Do Not Stuff

DIS_GM

R659

Do Not Stuff

DIS_GM

R233 Do Not Stuff

GNDREF

VDDREF

REF0/FSLC/TEST_SEL

SDATA

SCLK

PCI0/CR#_A

VDDPCI

PCI1/CR#_B

PCI2/TME

PCI3

PCI4/27_SELECT

PCI_F5/ITP_EN

GNDPCI

VDD48

USB_48MHZ/FSLA

GND48

VDD96_IO

SRCT0/DOTT_96

SRCC0/DOTC_96

GND

VDDPLL3

27MHZ_NONSS/SRCT1/SE1

27MHZ_SS/SRCC1/SE2

GND

VDDPLL3_IO

SRCT2/SATAT

SRCC2/SATAC

GNDSRC

SRCT3/CR#_C

SRCC3/CR#_D

VDDSRC_IO

SRCT4

SRCC4

GNDSRC

SRCT9

SRCC9

SRCC11/CR#_G

SRCT11/CR#_H

SRCT10

SRCC10

VDDSRC_IO

CPU_STOP#

PCI_STOP#

VDDSRC

SRCC6

SRCT6

GNDSRC

SRCC7/CR#_E

SRCT7/CR#_F

VDDSRC_IO

CPUC2_ITP/SRCC8

CPUT2_ITP/SRCT8

NC#55

VDDCPU_IO

CPUC1_F

CPUT1_F

GNDCPU

CPUC0

CPUT0

VDDCPU

CK_PWRGD/PD#

FSLB/TEST_MODE

GND

U15

ICS9LPRS365BKLFT-GP

1ST = 71.00875.A03

71.09365.A03

3RD = 71.08513.003

U15

ICS9LPRS365BKLFT-GP

1ST = 71.00875.A03

71.09365.A03

3RD = 71.08513.003

C250

SCD1U16V2ZY-2GP

C250

SCD1U16V2ZY-2GP

1 2

R657

Do Not Stuff

DIS_GM

R657

Do Not Stuff

DIS_GM

1 2

EC67

Do Not Stuff

EC67

Do Not Stuff

4 5

RN94

SRN470J-3-GP

RN94

SRN470J-3-GP

C253

SC4D7U10V5ZY-3GP

C253

SC4D7U10V5ZY-3GP

R201

Do Not Stuff

R201

Do Not Stuff

1 2

R202

Do Not Stuff

R202

Do Not Stuff

1 2

C229

SC27P50V2JN-2-GP

C229

SC27P50V2JN-2-GP

C225

SCD1U16V2ZY-2GP

C225

SCD1U16V2ZY-2GP

C255

SC1U16V3ZY-GP

C255

SC1U16V3ZY-GP

1 2

R660

Do Not Stuff

DIS_GM

R660

Do Not Stuff

DIS_GM

2 3

RN38

SRN0J-6-GP

UMA

RN38

SRN0J-6-GP

UMA

R213

Do Not Stuff

R213

Do Not Stuff

R243 33R2J-2-GPR243 33R2J-2-GP

RN91

SRN10KJ-6-GP

RN91

SRN10KJ-6-GP

C256

Do Not Stuff

C256

Do Not Stuff

4 5

RN92

SRN33J-7-GP

RN92

SRN33J-7-GP

R241 2K2R2J-2-GPR241 2K2R2J-2-GP

C217

SCD1U16V2ZY-2GP

C217

SCD1U16V2ZY-2GP

C223

SCD1U16V2ZY-2GP

C223

SCD1U16V2ZY-2GP

C221

SCD1U16V2ZY-2GP

C221

SCD1U16V2ZY-2GP

1 2

EC70

Do Not Stuff

EC70

Do Not Stuff

R211 33R2J-2-GPR211 33R2J-2-GP

1 2

EC101

Do Not Stuff

EC101

Do Not Stuff

RN93

SRN10KJ-6-GP

RN93

SRN10KJ-6-GP

4 4

3 3

2 2

1 1

H_A#18

H_A#20

H_A#21

H_A#22

H_A#17

H_A#19

H_A#23

H_A#24

H_A#25

H_A#26

H_A#27

H_A#28

H_A#29

H_A#30

H_A#31

H_A#3

H_A#4

H_A#5

H_A#6

H_A#7

H_A#8

H_A#9

H_A#10

H_A#11

H_A#12

H_A#13

H_A#14

H_A#15

H_A#16

H_REQ#0

H_REQ#1

H_REQ#2

H_REQ#3

H_REQ#4

H_A#[35..3]

H_RS#1

H_RS#0

H_RS#2

H_IERR#

XDP_BPM#0

XDP_BPM#1

XDP_BPM#2

XDP_BPM#3

XDP_BPM#4

XDP_TCK

XDP_TDI

XDP_TMS

XDP_TRST#

XDP_TDO

XDP_DBRESET#

THERMTRIP#

XDP_BPM#5

H_D#32

H_D#33

H_D#34

H_D#35

H_D#36

H_D#37

H_D#38

H_D#39

H_D#41

H_D#40

H_D#42

H_D#43

H_D#[63..0]

H_D#44

H_D#45

H_D#46

H_D#47

H_D#0

H_D#1

H_D#2

H_D#3

H_D#4

H_D#5

H_D#6

H_D#7

H_D#8

H_D#9

H_D#10

H_D#11

H_D#12

H_D#13

H_D#14

H_D#15

H_D#16

H_D#17

H_D#18

H_D#19

H_D#20

H_D#21

H_D#22

H_D#23

H_D#24

H_D#25

H_D#26

H_D#27

H_D#28

H_D#29

H_D#30

H_D#31

H_D#48

H_D#49

H_D#51

H_D#50

H_D#52

H_D#53

H_D#54

H_D#55

H_D#57

H_D#56

H_D#58

H_D#59

H_D#60

H_D#61

H_D#63

H_D#62

COMP0

COMP1

COMP2

COMP3

TEST1

TEST2

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_DINV#[3..0]

RSVD_CPU_12

RSVD_CPU_13

RSVD_CPU_14

XDP_TDI

XDP_TMS

XDP_TRST#

H_CPURST#

XDP_DBRESET#

XDP_TCK

H_THERMDC

H_THERMDA

CPU_GTLREF0

CPU_PROCHOT#

TEST4

TEST1

TEST2

TEST4

H_A#32

H_A#33

H_A#34

H_A#35

XDP_BPM#5

H_STPCLK#_R

1D05V_S0

3D3V_S0

H_ADS# 6

H_BNR# 6

H_DRDY# 6

H_DBSY# 6

H_BREQ#0 6

H_HIT# 6

H_HITM# 6

H_LOCK# 6

H_DSTBN#2 6

H_DSTBP#2 6

H_DINV#2 6

H_D#[63..0] 6

H_DSTBN#3 6

H_DSTBP#3 6

H_DINV#3 6

H_ADSTB#16

H_A#[35..3]6

H_ADSTB#06

H_REQ#[4..0]6

H_DSTBN#06

H_DSTBP#06

H_DINV#06

H_DSTBN#16

H_DSTBP#16

H_DINV#16

H_BPRI# 6

H_DEFER# 6

H_INIT# 21

H_CPURST# 6,55

H_RS#[2..0] 6

H_TRDY# 6

H_THERMDA 25

CLK_CPU_BCLK 3

CLK_CPU_BCLK# 3

H_DPRSTP# 7,21,48

H_DPSLP# 21

H_DPWR# 6

H_PWRGD 21,46,55

H_CPUSLP# 6

H_FERR#21

H_THERMDC 25

PM_THRMTRIP-A# 7,21,46

H_INTR21

H_NMI21

H_SMI#21

H_IGNNE#21

H_A20M#21

H_DINV#[3..0] 6

H_DSTBN#[3..0] 6

H_DSTBP#[3..0] 6

CPU_SEL23,7

CPU_SEL03,7

CPU_SEL13,7

H_STPCLK#21

PSI# 48

CPU_PROCHOT#_R 48

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

CPU (1 of 2)

457Thursday, April 03, 2008

Homa

-1

970

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

CPU (1 of 2)

457Thursday, April 03, 2008

Homa

-1

970

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

CPU (1 of 2)

457Thursday, April 03, 2008

Homa

-1

970

H_IERR# with a GND

0.1" away

Place testpoint on

Layout Note:

Comp0, 2 connect with Zo=27.4 ohm, make

Comp1, 3 connect with Zo=55 ohm, make

trace length shorter than 0.5" .

Layout Note:

"CPU_GTLREF0"

0.5" max length.

( No stub)

should connect to

PM_THRMTRIP#

without T-ing

ICH9 and MCH

All place within 2" to CPU

Net "TEST4" as short as possible,

make sure "TEST4" routing is

reference to GND and away other

noisy signals

R82

68R2-GP

R82

68R2-GP

TP13 Do Not StuffTP13 Do Not Stuff

TP7 Do Not StuffTP7 Do Not Stuff

1 2

R75

Do Not Stuff

R75

Do Not Stuff

C25

Do Not Stuff

C25

Do Not Stuff

TP9 Do Not StuffTP9 Do Not Stuff

1 2

R401 Do Not Stuff

D16#

N22

D17#

K25

D18#

P26

D19#

R23

D20#

L23

D21#

M24

D22#

L22

D23#

M23

D24#

P25

D25#

P23

D26#

P22

D27#

T24

D28#

R24

D29#

L25

D30#

T25

D31#

N25

DINV0#

H25

DINV1#

N24

DSTBN0#

J26

DSTBN1#

L26

DSTBP0#

H26

DSTBP1#

M26

D0#

E22

D1#

F24

D2#

E26

D3#

G22

D4#

F23

D5#

G25

D6#

E25

D7#

E23

D8#

K24

D9#

G24

D10#

J24

D11#

J23

D12#

H22

D13#

F26

D14#

K22

D15#

H23

D53#

AC26

D60#

AC22

D63#

AC23

GTLREF

AD26

TEST2

D25

BSEL0

B22

BSEL1

B23

BSEL2

C21

DINV2#

U22

D32#

Y22

D33#

AB24

D34#

V24

D35#

V26

D36#

V23

D38#

U25

D39#

U23

D40#

Y25

D41#

W22

D42#

Y23

D43#

W24

D44#

W25

D45#

AA23

D46#

AA24

D47#

AB25

DSTBP2#

AA26

DSTBN2#

Y26

D48#

AE24

D49#

AD24

D52#

AB21

D54#

AD20

D55#

AE22

D56#

AF23

D57#

AC25

D58#

AE21

D59#

AD21

D61#

AD23

DINV3#

AC20

DSTBN3#

AE25

D51#

AB22

D50#

AA21

D62#

AF22

COMP0

R26

COMP1

U26

DPRSTP#

DPSLP#

DPWR#

D24

PWRGOOD

SLP#

PSI#

AE6

TEST1

C23

TEST6

A26

TEST3

C24

TEST5

AF1

TEST4

AF26

D37#

T22

DSTBP3#

AF24

COMP2

AA1

COMP3

2 OF 4

DATA GRP0 DATA GRP1

DATA GRP2DATA GRP3

MISC

U29B

BGA479-SKT6-GPU6

1ST = 62.10053.401

2 OF 4

DATA GRP0 DATA GRP1

DATA GRP2DATA GRP3

MISC

U29B

BGA479-SKT6-GPU6

1ST = 62.10053.401

1 2

R53 54D9R2F-L1-GPR53 54D9R2F-L1-GP

TP14 Do Not StuffTP14 Do Not Stuff

1 2

R109 Do Not Stuff

1 2

R41

1KR2F-3-GP

R41

1KR2F-3-GP

TP15 Do Not StuffTP15 Do Not Stuff

TP12 Do Not StuffTP12 Do Not Stuff

TP16Do Not StuffTP16Do Not Stuff

1 2

R52 54D9R2F-L1-GPR52 54D9R2F-L1-GP

1 2

R66 27D4R2F-L1-GPR66 27D4R2F-L1-GP

A3#

A4#

A5#

A6#

A7#

A8#

A9#

A10#

A11#

A12#

A13#

A14#

A15#

A16#

A20M#

ADS#

ADSTB0#

REQ0#

REQ1#

REQ2#

REQ3#

REQ4#

A17#

A18#

A19#

A20#

A21#

A22#

A30#

A24#

A25#

A26#

A32#

A28#

A29#

A27#

A31#

A33#

AA4

A34#

AB2

A35#

AA3

FERR#

IGNNE#

RSVD#M4

RSVD#N5

RSVD#T2

RSVD#V3

RSVD#B2

RSVD#C3

BNR#

BPRI#

DEFER#

DBSY#

DRDY#

F21

BR0#

IERR#

D20

INIT#

LOCK#

RS0#

RS1#

RS2#

TRDY#

HIT#

HITM#

BPM0#

AD4

BPM1#

AD3

BPM2#

AD1

BPM3#

AC4

PRDY#

AC2

PREQ#

AC1

TCK

AC5

TDI

AA6

TDO

AB3

TMS

AB5

TRST#

AB6

DBR#

C20

PROCHOT#

D21

THRMDA

A24

THERMTRIP#

BCLK0

A22

BCLK1

A21

RSVD#D2

RSVD#F6

RSVD#D3

RSVD#D22

D22

STPCLK#

LINT0

LINT1

SMI#

A23#

ADSTB1#

RESET#

KEY_NC

THRMDC

B25

1 OF 4

RESERVED

HCLK

THERMAL

ADDR GROUP 1

XDP/ITP SIGNALS CONTROL

ADDR GROUP 0

ICH

U29A

BGA479-SKT6-GPU6

62.10079.001

1ST = 62.10053.401

1 OF 4

RESERVED

HCLK

THERMAL

ADDR GROUP 1

XDP/ITP SIGNALS CONTROL

ADDR GROUP 0

ICH

U29A

BGA479-SKT6-GPU6

62.10079.001

1ST = 62.10053.401

1 2

R59 54D9R2F-L1-GPR59 54D9R2F-L1-GP

TP8 Do Not StuffTP8 Do Not Stuff

TP11 Do Not StuffTP11 Do Not Stuff

C30

Do Not Stuff

C30

Do Not Stuff

TP10 Do Not StuffTP10 Do Not Stuff

TP21Do Not StuffTP21Do Not Stuff

TP5 Do Not StuffTP5 Do Not Stuff

1 2

R102 Do Not Stuff

TP3 Do Not StuffTP3 Do Not Stuff

C97

Do Not Stuff

C97

Do Not Stuff

TP17 Do Not StuffTP17 Do Not Stuff

1 2

R42 54D9R2F-L1-GPR42 54D9R2F-L1-GP

TP6 Do Not StuffTP6 Do Not Stuff

1 2

R48 27D4R2F-L1-GPR48 27D4R2F-L1-GP

TP18 Do Not StuffTP18 Do Not Stuff

1 2

R100

Do Not Stuff

R100

Do Not Stuff

1 2

R43 54D9R2F-L1-GPR43 54D9R2F-L1-GP

1 2

R54 54D9R2F-L1-GPR54 54D9R2F-L1-GP

1 2

R104

Do Not Stuff

R104

Do Not Stuff

R86

56R2J-4-GP

R86

56R2J-4-GP

R34

2KR2F-3-GP

R34

2KR2F-3-GP

1 2

R101 Do Not Stuff

1 2

R51 54D9R2F-L1-GPR51 54D9R2F-L1-GP

TP1Do Not StuffTP1Do Not Stuff

4 4

3 3

2 2

1 1

H_VID0

H_VID1

H_VID2

H_VID3

H_VID4

H_VID5

H_VID6

VCCP_1D05

VCC_CORE

1D5V_S0_R

1D05V_S0

1D5V_VCCA_S0

1D05V_S0

VCC_CORE

VCC_SENSE 48

VSS_SENSE 48

H_VID[6..0] 48

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

CPU (2 of 2)

557Thursday, April 03, 2008

Homa

-1

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

CPU (2 of 2)

557Thursday, April 03, 2008

Homa

-1

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

CPU (2 of 2)

557Thursday, April 03, 2008

Homa

-1

Layout Note:

should be of equal length.

VCCSENSE and VSSSENSE lines

Layout Note:

Provide a test point (with

no stub) to connect a

differential probe

between VCCSENSE and

VSSSENSE at the location

where the two 54.9ohm

resistors terminate the

55 ohm transmission line.

layout note: "1D5V_VCCA_S0"

as short as possible

C134

Do Not Stuff

C134

Do Not Stuff

C394

Do Not Stuff

C394

Do Not Stuff

TP20

Do Not Stuff

TP20

Do Not Stuff

C81

Do Not Stuff

C81

Do Not Stuff

C80

Do Not Stuff

C80

Do Not Stuff

TC15

Do Not Stuff

TC15

Do Not Stuff

C392

SC10U6D3V5MX-3GP

C392

SC10U6D3V5MX-3GP

C58

Do Not Stuff

C58

Do Not Stuff

C59

SCD1U10V2KX-4GP

C59

SCD1U10V2KX-4GP

C67

Do Not Stuff

C67

Do Not Stuff

1 2

G13

Do Not Stuff

G13

Do Not Stuff

C60

Do Not Stuff

C60

Do Not Stuff

VCC

AC10

VCC

A10

VCC

A12

VCC

A13

VCC

A15

VCC

A17

VCC

A18

VCC

A20

VCC

B10

VCC

B12

VCC

B14

VCC

B15

VCC

B17

VCC

B18

VCC

B20

VCC

C10

VCC

C12

VCC

C13

VCC

C15

VCC

C17

VCC

C18

VCC

D10

VCC

D12

VCC

D14

VCC

D15

VCC

D17

VCC

D18

VCC

E10

VCC

E12

VCC

E13

VCC

E15

VCC

AA7

VCC

AA9

VCC

AA10

VCC

AA12

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA18

VCC

AA20

VCC

AB9

VCC

AB12

VCC

AB14

VCC

AB15

VCC

AB17

VCC

AB18

VCC

E17

VCC

E18

VCC

E20

VCC

F10

VCC

F12

VCC

F14

VCC

F15

VCC

F17

VCC

F18

VCC

F20

VCC

AB20

VCC

AB7

VCC

AC7

VCC

AC9

VCC

AC12

VCC

AC13

VCC

AC15

VCC

AC17

VCC

AC18

VCC

AD7

VCC

AD9

VCC

AD10

VCC

AD12

VCC

AD14

VCC

AD15

VCC

AD17

VCC

AD18

VCC

AE9

VCC

AE10

VCC

AE12

VCC

AE13

VCC

AE15

VCC

AE17

VCC

AE18

VCC

AE20

VCC

AF9

VCC

AF10

VCC

AF12

VCC

AF14

VCC

AF15

VCC

AF17

VCC

AF18

VCC

AF20

VCCP

G21

VCCP

J21

VCCP

K21

VCCP

M21

VCCP

N21

VCCP

R21

VCCP

T21

VCCP

V21

VCCP

W21

VCCA

B26

VCCA

C26

VID0

AD6

VID6

AE2

VID4

AE3

VID2

AE5

VID5

AF3

VID3

AF4

VID1

AF5

VSSSENSE

AE7

VCCSENSE

AF7

VCC

AB10

3 OF 4

U29C

BGA479-SKT6-GPU6

1ST = 62.10053.401

3 OF 4

U29C

BGA479-SKT6-GPU6

1ST = 62.10053.401

C39

Do Not Stuff

C39

Do Not Stuff

R39

100R2F-L1-GP-U

R39

100R2F-L1-GP-U

1 2

HCB1608KF121T30-GP

68.00230.041

2ND = 68.00206.021

HCB1608KF121T30-GP

68.00230.041

2ND = 68.00206.021

C44

SCD1U10V2KX-4GP

C44

SCD1U10V2KX-4GP

R40

100R2F-L1-GP-U

R40

100R2F-L1-GP-U

C82

SC10U6D3V5MX-3GP

C82

SC10U6D3V5MX-3GP

C71

SCD1U10V2KX-4GP

C71

SCD1U10V2KX-4GP

C91

SCD01U16V2KX-3GP

C91

SCD01U16V2KX-3GP

C101

Do Not Stuff

C101

Do Not Stuff

C43

SC10U6D3V5MX-3GP

C43

SC10U6D3V5MX-3GP

VSS

AF2

VSS

A11

VSS

A14

VSS

A16

VSS

A19

VSS

A23

VSS

B11

VSS

B13

VSS

B16

VSS

B19

VSS

B21

VSS

B24

VSS

C11

VSS

C14

VSS

C16

VSS

C19

VSS

C22

VSS

C25

VSS

D11

VSS

D13

VSS

D16

VSS

D19

VSS

D23

VSS

D26

VSS

E11

VSS

E14

VSS

E16

VSS

E19

VSS

E21

VSS

E24

VSS

F11

VSS

F13

VSS

F16

VSS

F19

VSS

F22

VSS

F25

VSS

G23

VSS

G26

VSS

H21

VSS

H24

VSS

J22

VSS

J25

VSS

K23

VSS

K26

VSS

L21

VSS

L24

VSS

M22

VSS

M25

VSS

N23

VSS

N26

VSS

P21

VSS

P24

VSS

R22

VSS

R25

VSS

T23

VSS

T26

VSS

U21

VSS

U24

VSS

V22

VSS

V25

VSS

W23

VSS

W26

VSS

Y21

VSS

Y24

VSS

AA2

VSS

AA5

VSS

AA8

VSS

AA11

VSS

AA14

VSS

AA16

VSS

AA19

VSS

AA22

VSS

AA25

VSS

AB1

VSS

AB4

VSS

AB8

VSS

AB11

VSS

AB13

VSS

AB16

VSS

AB19

VSS

AB23

VSS

AB26

VSS

AC3

VSS

AC6

VSS

AC8

VSS

AC11

VSS

AC14

VSS

AC16

VSS

AC19

VSS

AC21

VSS

AC24

VSS

AD2

VSS

AD5

VSS

AD8

VSS

AD11

VSS

AD13

VSS

AD16

VSS

AD19

VSS

AD22

VSS

AD25

VSS

AE1

VSS

AE4

VSS

AE8

VSS

AE11

VSS

AE14

VSS

AE16

VSS

AE19

VSS

AE23

VSS

AE26

VSS

AF6

VSS

AF8

VSS

AF11

VSS

AF13

VSS

AF16

VSS

AF19

VSS

AF21

VSS

A25

VSS

AF25

4 OF 4

U29D

BGA479-SKT6-GPU6

1ST = 62.10053.401

4 OF 4

U29D

BGA479-SKT6-GPU6

1ST = 62.10053.401

C377

Do Not Stuff

C377

Do Not Stuff

C78

SC10U6D3V5MX-3GP

C78

SC10U6D3V5MX-3GP

C165

Do Not Stuff

C165

Do Not Stuff

C79

SCD1U10V2KX-4GP

C79

SCD1U10V2KX-4GP

C61

SC10U6D3V5MX-3GP

C61

SC10U6D3V5MX-3GP

C56

Do Not Stuff

C56

Do Not Stuff

C50

Do Not Stuff

C50

Do Not Stuff

C90

SC10U6D3V5MX-3GP

C90

SC10U6D3V5MX-3GP

C99

Do Not Stuff

C99

Do Not Stuff

C66

Do Not Stuff

C66

Do Not Stuff

C70

Do Not Stuff

C70

Do Not Stuff

C62

Do Not Stuff

C62

Do Not Stuff

TP2

Do Not Stuff

TP2

Do Not Stuff

C40

Do Not Stuff

C40

Do Not Stuff

TP19

Do Not Stuff

TP19

Do Not Stuff

TP4

Do Not Stuff

TP4

Do Not Stuff

C38

Do Not Stuff

C38

Do Not Stuff

C72

Do Not Stuff

C72

Do Not Stuff

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