山外K60库完整工程.zip

/* ** ################################################################### ** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** ** Reference manual: K70P256M150SF3RM, Rev. 0, May 2011 ** Version: rev. 1.1, 2011-08-12 ** ** Abstract: ** This header file implements peripheral memory map for MK70F15 ** processor. ** ** Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http: www.freescale.com ** mail: support@freescale.com ** ** Revisions: ** - rev. 1.0 (2011-07-01) ** Initial version. ** - rev. 1.1 (2011-08-12) ** DMA - base definition of DMA Channel Priority Registers changed from array to single registers. ** TSI - module changed to new version: A_IP_TouchSensor_LP_NN_C90LP_OPT. ** UART0 - LON control registers added ** ** ################################################################### */ /** * @file MK70F15.h * @version 1.1 * @date 2011-08-12 * @brief Peripheral memory map for MK70F15 * * This header file implements peripheral memory map for MK70F15 processor. */ /* ---------------------------------------------------------------------------- -- MCU activation ---------------------------------------------------------------------------- */ /* Prevention from multiple including the same memory map */ #if !defined(MCU_MK70F12) && !defined(MCU_MK70F15) /* Check if memory map has not been already included */ #define MCU_MK70F12 #define MCU_MK70F15 /* Check if another memory map has not been also included */ #if (defined(MCU_ACTIVE)) #error MK70F15 memory map: There is already included another memory map. Only one memory map can be included. #endif /* (defined(MCU_ACTIVE)) */ #define MCU_ACTIVE #include <stdint.h> /** Memory map version 1.1 */ #define MCU_MEM_MAP_VERSION 0x0101u /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. * @param Reg Register to access. * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ #define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /** * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ typedef enum { INT_Initial_Stack_Pointer = 0, /**< Initial stack pointer */ INT_Initial_Program_Counter = 1, /**< Initial program counter */ INT_NMI = 2, /**< Non-maskable interrupt */ INT_Hard_Fault = 3, /**< Hard fault exception */ INT_Mem_Manage_Fault = 4, /**< Memory Manage Fault */ INT_Bus_Fault = 5, /**< Bus fault exception */ INT_Usage_Fault = 6, /**< Usage fault exception */ INT_Reserved7 = 7, /**< Reserved interrupt 7 */ INT_Reserved8 = 8, /**< Reserved interrupt 8 */ INT_Reserved9 = 9, /**< Reserved interrupt 9 */ INT_Reserved10 = 10, /**< Reserved interrupt 10 */ INT_SVCall = 11, /**< A supervisor call exception */ INT_DebugMonitor = 12, /**< Debug Monitor */ INT_Reserved13 = 13, /**< Reserved interrupt 13 */ INT_PendableSrvReq = 14, /**< PendSV exception - request for system level service */ INT_SysTick = 15, /**< SysTick interrupt */ INT_DMA0_DMA16 = 16, /**< DMA channel 0/16 transfer complete interrupt */ INT_DMA1_DMA17 = 17, /**< DMA channel 1/17 transfer complete interrupt */ INT_DMA2_DMA18 = 18, /**< DMA channel 2/18 transfer complete interrupt */ INT_DMA3_DMA19 = 19, /**< DMA channel 3/19 transfer complete interrupt */ INT_DMA4_DMA20 = 20, /**< DMA channel 4/20 transfer complete interrupt */ INT_DMA5_DMA21 = 21, /**< DMA channel 5/21 transfer complete interrupt */ INT_DMA6_DMA22 = 22, /**< DMA channel 6/22 transfer complete interrupt */ INT_DMA7_DMA23 = 23, /**< DMA channel 7/23 transfer complete interrupt */ INT_DMA8_DMA24 = 24, /**< DMA channel 8/24 transfer complete interrupt */ INT_DMA9_DMA25 = 25, /**< DMA channel 9/25 transfer complete interrupt */ INT_DMA10_DMA26 = 26, /**< DMA channel 10/26 transfer complete interrupt */ INT_DMA11_DMA27 = 27, /**< DMA channel 11/27 transfer complete interrupt */ INT_DMA12_DMA28 = 28, /**< DMA channel 12/28 transfer complete interrupt */ INT_DMA13_DMA29 = 29, /**< DMA channel 13/29 transfer complete interrupt */ INT_DMA14_DMA30 = 30, /**< DMA channel 14/30 transfer complete interrupt */ INT_DMA15_DMA31 = 31, /**< DMA channel 15/31 transfer complete interrupt */ INT_DMA_Error = 32, /**< DMA error interrupt */ INT_MCM = 33, /**< Normal interrupt */ INT_FTFE = 34, /**< FTFE interrupt */ INT_Read_Collision = 35, /**< Read collision interrupt */ INT_LVD_LVW = 36, /**< Low Voltage Detect, Low Voltage Warning */ INT_LLW = 37, /**< Low Leakage Wakeup */ INT_Watchdog = 38, /**< WDOG interrupt */ INT_RNG = 39, /**< RNGA interrupt */ INT_I2C0 = 40, /**< I2C0 interrupt */ INT_I2C1 = 41, /**< I2C1 interrupt */ INT_SPI0 = 42, /**< SPI0 interrupt */ INT_SPI1 = 43, /**< SPI1 interrupt */ INT_SPI2 = 44, /**< SPI2 interrupt */ INT_CAN0_ORed_Message_buffer = 45, /**< CAN0 OR'd message buffers interrupt */ INT_CAN0_Bus_Off = 46, /**< CAN0 bus off interrupt */ INT_CAN0_Error = 47, /**< CAN0 error interrupt */ INT_CAN0_Tx_Warning = 48, /**< CAN0 Tx warning interrupt */ INT_CAN0_Rx_Warning = 49, /**< CAN0 Rx warning interrupt */ INT_CAN0_Wake_Up = 50, /**< CAN0 wake up interrupt */ INT_I2S0_Tx = 51, /**< I2S0 transmit interrupt */ INT_I2S0_Rx = 52, /**< I2S0 receive interrupt */ INT_CAN1_ORed_Message_buffer = 53, /**< CAN1 OR'd message buffers interrupt */ INT_CAN1_Bus_Off = 54, /**< CAN1 bus off interrupt */ INT_CAN1_Error = 55, /**< CAN1 error interrupt */ INT_CAN1_Tx_Warning = 56, /**< CAN1 Tx warning interrupt */ INT_CAN1_Rx_Warning = 57, /**< CAN1 Rx warning interrupt */