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题目:串行序列信号延时测试系统
摘要:本次课程设计为期两周,以之前学过的模电数电知识以及电工电子实
验相关内容等为基础,要求设计一串行序列信号测试系统。
课程设计的目的是通过这个课题,把所学的理论知识融入实践,即可以巩固所
学的理论知识,同时还可以在实践中认识不足。经由这次课题设计,让我们巩固加深
了之前所学的数模电知识,进一步提高了以前电工电子实验课程锻炼出来的动手实
践能力,电子电路设计、装配、调测、故障处理和文档整理等方面的能力,还能强
化我们的自学觉悟和能力,拓宽我们的眼界和实践技术知识。
而这次课题相对来说比较开放,没有什么固定死的要求,只要能完成系统所要
求的指标就可以了。当然还是有所限制的,本次课程设计不同以往,为了适应社会
要求,指导教师要求我们采用软件设计,在计算机上完成课程设计。我们所采用的
软件基本都是 ISE12.4,之所以说比较开放,是因为你可以采用任意方案或是途径来
完成:原理图,VHDL 语言,verilog 语言或是原理图和文本结合的方式。还有必要
的要求就是鼓励创新,严禁抄袭了。
说到这次课程设计的完成情况的话,有相当一部分人做出了成果,我也算是完
成了基本的技术指标,其中喜悦不言而喻。但遗憾的是部分结构还不够完善,需要
优化,提高指标并没能继续完成。总的来说还是喜悦居多,毕竟还是第一次完成一
个小型系统。总而言之,这次课题设计是一次艰辛而有意义,更有许多收获的过程,
受益匪浅。
关键词:课程设计 延时测试 同步数字系统 ISE
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TITLE:The Serial Sequence Signal Time Delay Test System
Summary: The course design lasts for two weeks, on the basis of the knowledge
of Analog electronic technology foundation , The digital circuit and system design and the
related content about Electrician electronic experiment technology .Asked to design a serial
sequence signal test system.
The purpose of the course design is to combine the theoretical knowledge into
practice, which can consolidate learning theory knowledge, at the same time we can know
the shortage of us. Through this project design ,we can know a lot about what we learned
before,let we deepen the analog electrical knowledge, to further improve the electrical and
electronic experimental course before exercise out hands-on practice ability, electronic
circuit design, assembly, test, the ability of fault handling and document finishing, etc, can
also strengthen our consciousness and the ability of self-study , broaden our horizon and
practical technical knowledge.
And this topic is relatively open, there is no fixed die, it’s okay as long as it can run.
It’s still limited, of course. The course design is different, in order to adapt to the social
requirement, guiding teacher asked us to use the software design, on the computer to
complete the course design. We adopted the software of basic ISE12.4, you can use any
way to achieve it: schematic diagram, VHDL language, verilog language or the principle of
combination of figure and text. And the necessary requirement is to encourage innovation,
copying is strictly prohibited.
When it comes to the completion of the course design of case, there are quite a
number of people made a result, I was completed the basic technical indicators, the joy is
self-evident. But it is a pity that part of the structure is not perfect enough, need to
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optimize, improve indicators and failed to continue to complete. In general or joy, after all,
is the first time to complete a small system. To sum up, this study design is a tough but
meaningful, there are many more harvest process, benefit a lot.
Keywords: Curriculum Design 、 Delay Test 、 Synchronous Digital
System、ISE
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目录(Contents)
目录(Contents).......................................................................................................................................4
第 1 章 技术指标........................................................................................................................................5
1.1 整体功能要求...............................................................................................................................5
1.2 系统结构.......................................................................................................................................5
1.3 技术指标.......................................................................................................................................5
第 2 章 整体方案设计................................................................................................................................6
2.1 方案论证.......................................................................................................................................6
2.2 系统设计.......................................................................................................................................6
第 3 章 单元电路设计................................................................................................................................8
3.1 控制器 VHDL 语言设计..............................................................................................................8
3.2 发送电路设计............................................................................................................................10
3.3 延迟电路设计............................................................................................................................12
3.4 接收电路的设计.........................................................................................................................13
3.5 延迟计算电路.............................................................................................................................15
3.6 分频器设计.................................................................................................................................17
3.7 五秒计数器的设计....................................................................................................................19
3.8 两秒计数器的设计.....................................................................................................................20
3.9 比较电路的设计.........................................................................................................................21
3.10 LED 显示电路的设计..............................................................................................................21
3.11 数码管显示电路的设计...........................................................................................................22
第 4 章 过程中的调测..............................................................................................................................24
4.1 管脚约束及元件下载.................................................................................................................24
4.2 出现问题及解决方案.................................................................................................................25
4.2.1 控制器部分.....................................................................................................................25
4.2.2 发送电路.........................................................................................................................27
4.2.3 接收电路.........................................................................................................................27
4.2.4 延迟判断电路.................................................................................................................28
4.2.5 计数电路部分.................................................................................................................28
4.2.6 比较电路.........................................................................................................................29
4.2.7 分频电路.........................................................................................................................30
4.2.8 整体电路.........................................................................................................................31
第 5 章 结束语..........................................................................................................................................32
【附录一】整体电路图及仿真...............................................................................................................35
【附录二】成果图...................................................................................................................................36
【附录三】ISE 原理图设计 部分相关元件及其功能..........................................................................39
【附录 四 】 预习报告及参考文献 ........................................................................................................... 39
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第 1 章 技术指标
1.1 整体功能要求
串行序列信号延时测试电路的功能是,由本测试系统送出一串串行序列信号,该
串行序列信号送出后经过线路传输产生一定时间的延迟再返回到本系统,系统收到信号
后判断是否为本系统发送的信号,若是,则同时测量出信号在传输过程中延迟的时间并
显示出来。
1.2 系统结构
该系统的基本结构如图 1-1 所示。
图 1-1 串行序列信号延时测试系统基本框图
图中按键手工控制,每按一下,发送电路就送出一串(8 个 bite)序列信号。发送
电路发送的码型由码型设置电路设置。线路延迟模拟电路用于模拟线路的延时情况。接
收电路用于判断是否收到了串行序列信号,判断延迟时间,判断串行序列码的码型是否
正确。延迟显示电路用于显示接收电路测出的延时时间。码型显示电路用于显示接收电
路测出的序列号的码型。如果判断不正确,发出报警信号。
1.3 技术指标
(1)按键采用自复键,每按一次给发送电路一个触发信号,连续两次触发信号的
时间间隔应大于 5s。
(2)手工设置发送串行序列码型,序列码 M=8。
按键
发送电路
线路延迟
模拟电路
接收电路
码型
设置
延迟
显示
码型
显示
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