digital-clock.rar_VHDL/FPGA/Verilog_VHDL_
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2021-08-11
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digital-clock.rar （79个子文件） 
digital clock 
.lso 6B sw.ucf 0B sw.cmd_log 4KB stopwatch.ntrc_log 918B sw.syr 5KB xst work sub00 vhpl01.vho 3KB vhpl00.vho 1KB hdpdeps.ref 576B hdllib.ref 224B dump.xst sw.prj ngx opt notopt ntrc.scr 1KB projnav.tmp sw.prj 20B _xmsgs xst.xmsgs 557B pepExtractor.prj 13B
sw_summary.html 3KB sw_xst.xrpt 788B sw.spl 95B stopwatch.ise 148KB sw_vhdl.prj 84B sw.xst 1KB stopwatch.restore 54KB sw.vhd 2KB sw.lfp 0B stopwatch_xdb cst.xbcd 115B tmp ise version 138B __OBJSTORE__ xreport Gc_RvReportViewer-Current-Module 27B Gc_RvReportViewer-Module-Data-sw_StrTbl 10KB Gc_RvReportViewer-Module-DataFactory-Default 297B Gc_RvReportViewer-Module-Data-sw 293B Gc_RvReportViewer-Module-DataFactory-Default_StrTbl 10KB Gc_RvReportViewer-Current-Module_StrTbl 14B PnAutoRun Scripts RunOnce_tcl 27B RunOnce_tcl_StrTbl 4KB ProjectNavigatorGui GuiProjectData 216B GuiProjectData_StrTbl 347B ProjectNavigator __stored_object_table__ 43KB __stored_objects___StrTbl 20KB dpm_project_main dpm_project_main 82B dpm_project_main_StrTbl 53B __stored_objects__ 51KB STE common _ProjRepoInternal_ HierarchicalDesign __stored_object_table__ 60B HDProject HDProject_StrTbl 19B HDProject 201B SrcCtrl SavedOptions Autonym __REGISTRY__ cpldfit regkeys 47B vhpcomp regkeys 47B xreport regkeys 0B tsim regkeys 44B netgen regkeys 46B runner regkeys 46B xpwr regkeys 44B ProjectNavigatorGui regkeys 0B xst regkeys 43B trce regkeys 44B idem regkeys 44B dumpngdio regkeys 49B map regkeys 43B ProjectNavigator regkeys 35B STE xst regkeys 519B regkeys 44B vlogcomp regkeys 48B bitgen regkeys 46B ngc2edif regkeys 48B XSLTProcess regkeys 51B common regkeys 173B _ProjRepoInternal_ regkeys 266B hprep6 regkeys 46B HierarchicalDesign HDProject regkeys 159B regkeys 0B par regkeys 43B SrcCtrl regkeys 0B taengine regkeys 48B Cs regkeys 0B fuse regkeys 44B ngcbuild regkeys 48B Autonym regkeys 0B ngdbuild regkeys 48B ise.lock 158B sw.lso 6B sw.sym 1KB sw.vhi 765B资源评论
