IBM PPC440
Version 1.0 BIST for CAMRAM and UTLB macros
BIST_0_FuncSpecTOC.fm
September 9, 2003 - IBM Confidential
Page 5 of 37
1. Overview ...................................................................................................................... 3
2. Macro Block Diagram ................................................................................................. 5
3. Macro Pins Definitions: .............................................................................................. 7
3.1. Input Pins ........................................................................................................................................ 7
3.1.1. Clocks ..................................................................................................................................... 7
3.1.2. Data Inputs ............................................................................................................................. 7
3.2. Output pins ..................................................................................................................................... 8
3.2.1. DCA controls .......................................................................................................................... 8
3.2.2. ICA controls ............................................................................................................................ 8
3.2.3. MMU controls ......................................................................................................................... 8
3.2.4. Shared controls ...................................................................................................................... 8
3.2.5. BIST Pass/Fail Outputs .......................................................................................................... 9
4. BIST Clocking ............................................................................................................ 11
5. BIST Operation .......................................................................................................... 13
5.1. Registers Initialization ................................................................................................................. 14
5.1.1. dp_BIST_stuff1_regL2 register: ........................................................................................... 15
5.1.2. dp_BIST_stuff2_regL2 register: ............................................................................................ 16
5.1.3. dp_BIST_stuff3_regL2 register: ............................................................................................ 17
5.1.4. dp_BIST_Err1_regL2 register: .............................................................................................. 17
5.1.5. dp_BIST_Err2_regL2 register: .............................................................................................. 18
5.2. Running the BIST Test ................................................................................................................. 19
5.3. BIST TIMINGS ............................................................................................................................... 19
6. Test and Verification: ............................................................................................... 21
6.1. BIST State Machine ...................................................................................................................... 21
6.2. Manufacturing Test: ..................................................................................................................... 22
6.2.1. RAM Tests ............................................................................................................................ 22
6.2.2. CAM Tests ............................................................................................................................ 24
6.3. EVS Testing: ................................................................................................................................. 26
6.3.1. START2CH: .......................................................................................................................... 26
6.3.2. CH2RCH: .............................................................................................................................. 26
6.3.3. RCH2END:. .......................................................................................................................... 26
6.4. Burn_In Test ................................................................................................................................. 26
7. Error Reporting ......................................................................................................... 27
7.1. ABIST Error ................................................................................................................................... 27
7.2. CBIST Error ................................................................................................................................... 28
8. Diagnosis ................................................................................................................... 29
9. BIST to Memories connexions ................................................................................. 31
10. Related Documents ................................................................................................ 35
