Built-In
Self-Test
Techniques
BIST
allows
thorough
testing
at
reasonable
cost.
The
chip
overhead
due
to
BIST
can
be
minimized
by
a
wise
choice
of
implementation
techniques.
Edward
J.
McCluskey,
Stanford
University
Testing
a
circuit
requires
the
ap-
plication
of
a
test
stimulus
and
the
comparison
of
the
actual
circuit
response
with
the
correct
response.
General-purpose
testers,
though
com-
monly
used
for
this
purpose,
are
very
expensive;
and
tester
cost
is
not
the
only
difficulty
encountered
in
using
an
external
tester.
There
are
also
prob-
lems
with:
(1)
Time.
The
turnaround
time
to
generate
test
patterns,
the
time
taken
to
apply
the
test
patterns,
and
the
com-
putation
time
are
growing
too
large.
(2)
Volume.
The
number
of
test
patterns
is
becoming
too
large
to
be
handled
efficiently
by
the
tester
hard-
ware.
Several
techniques
have
been
pro-
posed
for
reducing
the
complexity
of
external
testing
by
moving
some
or
all
of
the
tester
functions
onto
the
chip
itself
or
onto
the
board
on
which
the
chips
are
mounted.
This
article
pre-
sents
techniques
for
generating
test
patterns
and
evaluating
output
re-
sponses
in
built-in
self
test
designs.
These
techniques
are
intended
to
solve
the
problems
listed
above
as
well
as
to
reduce
the
tester
cost.
A
companion
article,
"Built-In
Self-Test
Struc-
tures,"
discusses
the
structures
used
to
integrate
the
test
and
functional
cir-
cuitry
(see
pp.
29-36
this
issue).
General
BIST
attributes.
The
inclu-
sion
of
on-chip
circuitry
for
testing
is
called
"built-in
self
test"
(BIST),
"built-in
test'
(BIT),
"self
test,"
''autonomous
test,'
''in-situ
test,"
or
"self-verification."
There
is
some
am-
biguity
in
the
use
of
these
terms.
In
particular,
BIT
and
self-test
are
sometimes
used
to
mean
implicit
testing
(concurrent
checking
or
moni-
toring)
or
system-level,
periodic
testing.'
The
discussion
here
is
re-
stricted
to
explicit
test
(wafer
sort,
pro-
duction
test,
board
test,
maintenance
test,
repair
test)
techniques.
Any
test
method
must
consist
of:
(1)
a
strategy
for
generating
the
inputs
to
be
applied,
(2)
a
strategy
for
evaluating
the
output
responses,
and
(3)
the
im-
plementation
mechanisms.
This
arti-
cle
presents
a
survey
of
the
different
techniques
available
for
each
of
these
items.
Table
I
lists
the
most
important
at-
tributes
for
evaluating
BIST
struc-
tures.
All
techniques
must
be
able
to
detect
single
stuck
faults
in
the
func-
tional
circuitry.
Most
methods
can
detect
some
other
faults
as
well.
Ex-
0740-7475/85/0400-0021$01.00
1985
IEEE
VZ
April
1985
21
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