5.3.3 Machine Interrupt Enable (mie) .........................................................................21
5.3.4 Machine Interrupt Pending (mip) .......................................................................22
5.3.5 Machine Cause (mcause) .................................................................................22
5.4 Supervisor Mode Interrupts........................................................................................23
5.4.1 Delegation Registers (m*deleg) .......................................................................24
5.4.2 Supervisor Status Register (sstatus)...............................................................25
5.4.3 Supervisor Interrupt Enable Register (sie).........................................................26
5.4.4 Supervisor Interrupt Pending (sip) ....................................................................26
5.4.5 Supervisor Cause Register (scause).................................................................27
5.4.6 Supervisor Trap Vector (stvec) ........................................................................28
5.4.7 Delegated Interrupt Handling.............................................................................29
5.5 Interrupt Priorities .....................................................................................................30
5.6 Interrupt Latency.......................................................................................................30
6 Core-Local Interruptor (CLINT).....................................................................31
6.1 CLINT Memory Map..................................................................................................31
6.2 MSIP Registers.........................................................................................................31
6.3 Timer Registers ........................................................................................................32
6.4 Supervisor Mode Delegation ......................................................................................32
7 Level 2 Cache Controller .................................................................................33
7.1 Level 2 Cache Controller Overview.............................................................................33
7.2 Functional Description...............................................................................................33
7.2.1 Way Enable and the L2 Loosely Integrated Memory (L2-LIM) ...............................34
7.2.2 Way Masking and Locking.................................................................................35
7.2.3 L2 Scratchpad..................................................................................................35
7.2.4 Error Correcting Codes (ECC) ...........................................................................36
7.3 Memory Map ............................................................................................................36
7.4 Register Descriptions ................................................................................................37
7.4.1 Cache Configuration Register (Config).............................................................38
7.4.2 Way Enable Register (WayEnable) ...................................................................38
7.4.3 ECC Error Injection Register (ECCInjectError)...............................................38
7.4.4 ECC Directory Fix Address (DirECCFix*).........................................................39
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