5.3.1 Machine Status Register (mstatus) ..................................................................18
5.3.2 Machine Trap Vector (mtvec)............................................................................18
5.3.3 Machine Interrupt Enable (mie) .........................................................................20
5.3.4 Machine Interrupt Pending (mip) .......................................................................21
5.3.5 Machine Cause (mcause) .................................................................................21
5.3.6 Machine Trap Vector Table (mtvt) .....................................................................23
5.3.7 Handler Address and Interrupt-Enable (mnxti)...................................................23
5.3.8 Machine Interrupt Status (mintstatus) ............................................................24
5.4 Interrupt Latency.......................................................................................................24
6 Core-Local Interrupt Controller (CLIC).....................................................25
6.1 Interrupt Sources ......................................................................................................25
6.2 CLIC Memory Map....................................................................................................26
6.3 Registers ................................................................................................................. 26
6.3.1 CLIC Interrupt Pending (clicintip) ................................................................27
6.3.2 CLIC Interrupt Enable (clicintie) ..................................................................27
6.3.3 CLIC Interrupt Configuration (clicintcfg) .......................................................27
6.3.4 CLIC Configuration (cliccfg) ..........................................................................28
7 Debug......................................................................................................................... 30
7.1 Debug CSRs ............................................................................................................30
7.1.1 Trace and Debug Register Select (tselect)......................................................30
7.1.2 Trace and Debug Data Registers (tdata1-3) ....................................................31
7.1.3 Debug Control and Status Register (dcsr) .........................................................32
7.1.4 Debug PC dpc.................................................................................................32
7.1.5 Debug Scratch dscratch ................................................................................32
7.2 Breakpoints ..............................................................................................................32
7.2.1 Breakpoint Match Control Register mcontrol ....................................................32
7.2.2 Breakpoint Match Address Register (maddress) ................................................34
7.2.3 Breakpoint Execution........................................................................................34
7.2.4 Sharing Breakpoints Between Debug and Machine Mode ....................................35
7.3 Debug Memory Map..................................................................................................35
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