6.5 Functional Description...............................................................................................14
6.5.1 Atomic Memory Operations (AMO) ....................................................................14
6.5.2 Bursts ............................................................................................................. 14
6.5.3 TL2AHB System Integration ..............................................................................15
7 Debug Interface..................................................................................................... 18
7.1 JTAG TAPC State Machine ........................................................................................19
7.2 Resetting JTAG Logic................................................................................................19
7.3 JTAG Clocking..........................................................................................................20
7.4 JTAG Standard Instructions .......................................................................................20
7.5 JTAG Debug Commands ...........................................................................................20
7.6 Using Debug Outputs ................................................................................................20
8 Implementation .....................................................................................................21
8.1 Top Level .................................................................................................................21
8.2 Clocking...................................................................................................................21
8.2.1 Clocking Guidelines..........................................................................................22
8.3 Retiming ..................................................................................................................22
8.4 Gate Level Simulation ...............................................................................................22
9 Simulation Testbench........................................................................................24
9.1 Included Test Bench..................................................................................................24
9.1.1 Executing the Testbench ...................................................................................24
9.2 Testbench Output......................................................................................................25
9.2.1 Testbench Output - Trace..................................................................................25
9.2.2 Testbench Output - Waves ................................................................................25
9.2.3 Adding Tests To The Included Testbench............................................................26
9.3 SiFive Insight............................................................................................................26
9.3.1 Viewing SiFive Insight Signals ...........................................................................27
9.3.2 Enabling SiFive Insight Outside of the SiFive Testbench ......................................27
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